Add TI OMAP watchdog timer driver.
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jmcneill
parent
c5154900d0
commit
963b86d431
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@ -1,4 +1,4 @@
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/* $NetBSD: am3_prcm.c,v 1.11 2019/11/27 23:02:54 jmcneill Exp $ */
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/* $NetBSD: am3_prcm.c,v 1.12 2019/11/29 20:54:00 jmcneill Exp $ */
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/*-
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* Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
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@ -28,7 +28,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.11 2019/11/27 23:02:54 jmcneill Exp $");
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__KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.12 2019/11/29 20:54:00 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -169,6 +169,8 @@ static struct ti_prcm_clk am3_prcm_clks[] = {
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AM3_PRCM_HWMOD_PER("timer6", 0xf0, "FIXED_24MHZ"),
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AM3_PRCM_HWMOD_PER("timer7", 0x7c, "FIXED_24MHZ"),
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AM3_PRCM_HWMOD_WKUP("wd_timer2", 0xd4, "FIXED_32K"),
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AM3_PRCM_HWMOD_PER("mmc1", 0x3c, "MMC_CLK"),
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AM3_PRCM_HWMOD_PER("mmc2", 0xf4, "MMC_CLK"),
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AM3_PRCM_HWMOD_PER("mmc3", 0xf8, "MMC_CLK"),
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@ -1,4 +1,4 @@
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# $NetBSD: files.ti,v 1.20 2019/11/03 22:59:06 jmcneill Exp $
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# $NetBSD: files.ti,v 1.21 2019/11/29 20:54:00 jmcneill Exp $
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#
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file arch/arm/ti/ti_cpufreq.c soc_ti
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@ -131,6 +131,11 @@ device omapnand: nandbus
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attach omapnand at fdt
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file arch/arm/ti/omap2_nand.c omapnand
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# Watchdog timer
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device tiwdt: sysmon_wdog
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attach tiwdt at fdt with ti_wdt
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file arch/arm/ti/ti_wdt.c ti_wdt
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# SOC parameters
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defflag opt_soc.h SOC_TI
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defflag opt_soc.h SOC_AM33XX: SOC_TI
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@ -0,0 +1,259 @@
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/* $NetBSD: ti_wdt.c,v 1.1 2019/11/29 20:54:00 jmcneill Exp $ */
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/*-
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* Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ti_wdt.c,v 1.1 2019/11/29 20:54:00 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/wdog.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <dev/fdt/fdtvar.h>
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#include <arm/ti/ti_prcm.h>
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#define WDT_WDSC 0x10
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#define WDSC_SOFTRESET __BIT(1)
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#define WDT_WDST 0x14
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#define WDT_WISR 0x18
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#define WDT_WIER 0x1c
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#define WDT_WCLR 0x24
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#define WCLR_PRE __BIT(5)
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#define WCLR_PTV __BITS(4,2)
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#define WDT_WCRR 0x28
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#define WDT_WLDR 0x2c
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#define WDT_WTGR 0x30
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#define WDT_WWPS 0x34
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#define WWPS_W_PEND_WDLY __BIT(5)
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#define WWPS_W_PEND_WSPR __BIT(4)
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#define WWPS_W_PEND_WTGR __BIT(3)
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#define WWPS_W_PEND_WLDR __BIT(2)
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#define WWPS_W_PEND_WCRR __BIT(1)
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#define WWPS_W_PEND_WCLR __BIT(0)
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#define WWPS_W_PEND_MASK __BITS(5,0)
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#define WDT_WDLY 0x44
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#define WDT_WSPR 0x48
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#define WDT_WIRQSTATRAW 0x54
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#define WDT_WIRQSTAT 0x58
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#define WDT_WIRQENSET 0x5c
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#define WDT_WIRQENCLR 0x60
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#define WIRQ_EVENT_DLY __BIT(1)
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#define WIRQ_EVENT_OVF __BIT(0)
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#define WATCHDOG_PERIOD_DEFAULT 10
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static const char * compatible[] = {
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"ti,omap3-wdt",
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NULL
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};
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struct ti_wdt_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct sysmon_wdog sc_wdog;
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u_int sc_rate;
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};
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#define RD4(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define WR4(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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static void
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ti_wdt_sync(struct ti_wdt_softc *sc, uint32_t mask)
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{
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uint32_t val;
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int retry;
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for (retry = 10000; retry > 0; retry--) {
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val = RD4(sc, WDT_WWPS);
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if ((val & mask) == 0)
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return;
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}
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aprint_error_dev(sc->sc_dev,
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"reg sync timeout, mask=%#x, wwps=%#x\n", mask, val);
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}
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static void
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ti_wdt_sync_all(struct ti_wdt_softc *sc)
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{
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ti_wdt_sync(sc, WWPS_W_PEND_MASK);
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}
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static int
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ti_wdt_reset(struct ti_wdt_softc *sc)
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{
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uint32_t val;
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int retry;
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val = RD4(sc, WDT_WDSC);
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val |= WDSC_SOFTRESET;
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WR4(sc, WDT_WDSC, val);
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for (retry = 10000; retry > 0; retry--) {
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val = RD4(sc, WDT_WDSC);
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if ((val & WDSC_SOFTRESET) == 0)
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return 0;
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delay(10);
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}
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return EIO;
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}
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static void
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ti_wdt_stop(struct ti_wdt_softc *sc)
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{
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WR4(sc, WDT_WSPR, 0xaaaa);
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ti_wdt_sync(sc, WWPS_W_PEND_WSPR);
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WR4(sc, WDT_WSPR, 0x5555);
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ti_wdt_sync(sc, WWPS_W_PEND_WSPR);
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}
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static void
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ti_wdt_start(struct ti_wdt_softc *sc)
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{
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WR4(sc, WDT_WSPR, 0xbbbb);
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ti_wdt_sync(sc, WWPS_W_PEND_WSPR);
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WR4(sc, WDT_WSPR, 0x4444);
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ti_wdt_sync(sc, WWPS_W_PEND_WSPR);
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}
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static int
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ti_wdt_setmode(struct sysmon_wdog *smw)
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{
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struct ti_wdt_softc * const sc = smw->smw_cookie;
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uint32_t counter_val;
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
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ti_wdt_stop(sc);
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return 0;
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}
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if (smw->smw_period == WDOG_PERIOD_DEFAULT)
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sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
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else
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sc->sc_wdog.smw_period = smw->smw_period;
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if (sc->sc_wdog.smw_period == 0)
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counter_val = ~0u;
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else
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counter_val = ~(sc->sc_wdog.smw_period * sc->sc_rate / 2);
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ti_wdt_stop(sc);
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ti_wdt_sync_all(sc);
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WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV));
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WR4(sc, WDT_WLDR, counter_val);
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WR4(sc, WDT_WCRR, counter_val);
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ti_wdt_sync_all(sc);
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ti_wdt_start(sc);
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return 0;
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}
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static int
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ti_wdt_tickle(struct sysmon_wdog *smw)
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{
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struct ti_wdt_softc * const sc = smw->smw_cookie;
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uint32_t val;
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ti_wdt_sync_all(sc);
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val = RD4(sc, WDT_WTGR);
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WR4(sc, WDT_WTGR, ~val);
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return 0;
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}
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static int
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ti_wdt_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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}
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static void
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ti_wdt_attach(device_t parent, device_t self, void *aux)
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{
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struct ti_wdt_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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struct clk *clk;
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bus_addr_t addr;
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bus_size_t size;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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clk = ti_prcm_get_hwmod(phandle, 0);
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if (clk == NULL || clk_enable(clk) != 0) {
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aprint_error(": couldn't enable hwmod\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_bst = faa->faa_bst;
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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sc->sc_rate = clk_get_rate(clk);
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aprint_naive("\n");
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aprint_normal(": WATCHDOG\n");
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/* Software reset */
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if (ti_wdt_reset(sc) != 0) {
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aprint_error_dev(self, "software reset timeout\n");
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return;
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}
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/* Stop the watchdog */
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ti_wdt_stop(sc);
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/* Register watchdog */
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sc->sc_wdog.smw_name = device_xname(self);
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sc->sc_wdog.smw_setmode = ti_wdt_setmode;
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sc->sc_wdog.smw_tickle = ti_wdt_tickle;
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sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
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sc->sc_wdog.smw_cookie = sc;
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sysmon_wdog_register(&sc->sc_wdog);
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}
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CFATTACH_DECL_NEW(ti_wdt, sizeof(struct ti_wdt_softc),
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ti_wdt_match, ti_wdt_attach, NULL, NULL);
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