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/* $NetBSD: psl.h,v 1.4 2005/12/11 12:17:37 christos Exp $ */
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/* $NetBSD: psl.h,v 1.5 2008/01/18 09:42:12 skrll Exp $ */
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/* $OpenBSD: psl.h,v 1.6 1999/11/25 18:29:01 mickey Exp $ */
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#define PSW_Y_POS (0)
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#define PSW_Z_POS (1)
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#define PSW_SS_POS (3) /* Reserved, Software-defined */
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#define PSW_W_POS (4)
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#define PSW_E_POS (5)
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#define PSW_S_POS (6)
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#define PSW_T_POS (7)
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#define PSW_V_POS (14)
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#define PSW_M_POS (15)
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#define PSW_CB_POS (16)
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#define PSW_O_POS (24)
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#define PSW_G_POS (25)
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#define PSW_F_POS (26)
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#define PSW_R_POS (27)
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#define PSW_D_POS (30)
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#define PSW_I_POS (31)
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#define PSW_BITS "\020\001I\002D\003P\004Q\005R\006F\007G" \
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#define PSW_BITS "\020\001I\002D\003P\004Q\005R\006F\007G\010O" \
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"\021M\022V\023C\024B\025X\026N\027L\030H" \
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"\031T\032S\033E\037Z\040Y"
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"\031T\032S\033E\034W\037Z\040Y"
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/*
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* Processor Status Word Bit Values
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#define PSW_Y (1 << (31-PSW_Y_POS)) /* Data Debug Trap Disable */
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#define PSW_Z (1 << (31-PSW_Z_POS)) /* Instruction Debug Trap Disable */
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#define PSW_SS (1 << (31-PSW_SS_POS)) /* Reserved; Software Single-Step */
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#define PSW_W (1 << (31-PSW_W_POS)) /* 64bit address decode enable */
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#define PSW_E (1 << (31-PSW_E_POS)) /* Little Endian Memory Access Enable */
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#define PSW_S (1 << (31-PSW_S_POS)) /* Secure Interval Timer */
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#define PSW_T (1 << (31-PSW_T_POS)) /* Taken Branch Trap Enable */
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#define PSW_V (1 << (31-PSW_V_POS)) /* Divide Step Correction */
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#define PSW_M (1 << (31-PSW_M_POS)) /* High-priority Machine Check Mask */
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#define PSW_CB (1 << (31-PSW_CB_POS)) /* Carry/Borrow Bits */
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#define PSW_O (1 << (31-PSW_O_POS)) /* Force strong ordering (2.0) */
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#define PSW_G (1 << (31-PSW_G_POS)) /* Debug Trap Enable */
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#define PSW_F (1 << (31-PSW_F_POS)) /* Perfomance Monitor Interrupt Unmask */
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#define PSW_R (1 << (31-PSW_R_POS)) /* Recover Counter Enable */
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