Properly compute the region sizes in pci_conf_print(). Bug pointed out
by Chris Demetriou.
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parent
38f367e1a0
commit
93db65c28c
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.23 1998/04/20 14:16:26 drochner Exp $ */
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/* $NetBSD: pci_subr.c,v 1.24 1998/05/03 19:41:33 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -41,6 +41,8 @@
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/intr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#ifdef PCIVERBOSE
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@ -320,8 +322,8 @@ pci_conf_print(pc, tag)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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{
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pcireg_t rval;
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int reg;
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pcireg_t rval, mask;
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int reg, s;
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#ifdef PCIVERBOSE
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struct pci_knowndev *kdp;
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static const char on_str[] = "ON", off_str[] = "OFF";
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@ -444,12 +446,28 @@ pci_conf_print(pc, tag)
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printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval));
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for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
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/*
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* Section 6.2.5.1, `Address Maps', tells us that:
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*
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* 1) The builtin software should have already mapped the
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* device in a reasonable way.
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*
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* 2) A device which wants 2^n bytes of memory will hardwire
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* the bottom n bits of the address to 0. As recommended,
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* we write all 1s and see what we get back.
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*/
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s = splhigh();
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rval = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, 0xffffffff);
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mask = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, rval);
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splx(s);
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printf(" Mapping register 0x%02x\n", reg);
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if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
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printf(" Base Address: 0x%08x, size 0x%08x, "
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"type = mem", PCI_MAPREG_MEM_ADDR(rval),
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PCI_MAPREG_MEM_SIZE(rval));
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PCI_MAPREG_MEM_SIZE(mask));
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switch (PCI_MAPREG_MEM_TYPE(rval)) {
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case PCI_MAPREG_MEM_TYPE_32BIT:
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printf(", 32-bit");
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@ -469,7 +487,7 @@ pci_conf_print(pc, tag)
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} else {
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printf(" Base Address: 0x%08x, size 0x%08x, "
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"type = i/o\n", PCI_MAPREG_IO_ADDR(rval),
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PCI_MAPREG_IO_SIZE(rval));
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PCI_MAPREG_IO_SIZE(mask));
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}
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}
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