New SCSI driver for the NCR5380, by David Jones.
Does DMA with interrupts. Much faster than our old driver which did only PIO transfers. (Thanks David!) Could be used on the amiga, and probably others...
This commit is contained in:
gwr
parent
28426ef703
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93d0f65970
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@ -1,4 +1,4 @@
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# $NetBSD: files.sun3,v 1.13 1995/10/10 21:25:29 gwr Exp $
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# $NetBSD: files.sun3,v 1.14 1995/10/29 21:21:19 gwr Exp $
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#
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# sun3-specific configuration info
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@ -95,6 +95,12 @@ file arch/sun3/dev/if_le_subr.c le
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device si at obio, vmes: scsi
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file arch/sun3/dev/si.c si
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define ncr5380sbc
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file arch/sun3/dev/ncr5380sbc.c ncr5380sbc
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device ncr_si at obio, vmes: scsi, ncr5380sbc
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file arch/sun3/dev/ncr_si.c ncr_si
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#
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# On-Board MEMory (OBMEM)
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#
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@ -0,0 +1,83 @@
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/* $NetBSD: am9516.h,v 1.1 1995/10/29 21:19:06 gwr Exp $ */
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/*
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* This file is derived from the file dev/devSCSI3.c from
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* the Berkeley SPRITE distribution, which says:
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*
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* Copyright 1988 Regents of the University of California
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. The University of California
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* AMD 9516 UDC (Universal DMA Controller) Registers.
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* This is used only in the OBIO version (3/50,3/60).
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*/
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/* addresses of the udc registers accessed directly by driver */
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#define UDC_ADR_MODE 0x38 /* master mode register */
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#define UDC_ADR_COMMAND 0x2e /* command register (write only) */
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#define UDC_ADR_STATUS 0x2e /* status register (read only) */
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#define UDC_ADR_CAR_HIGH 0x26 /* chain addr reg, high word */
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#define UDC_ADR_CAR_LOW 0x22 /* chain addr reg, low word */
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#define UDC_ADR_CARA_HIGH 0x1a /* cur addr reg A, high word */
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#define UDC_ADR_CARA_LOW 0x0a /* cur addr reg A, low word */
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#define UDC_ADR_CARB_HIGH 0x12 /* cur addr reg B, high word */
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#define UDC_ADR_CARB_LOW 0x02 /* cur addr reg B, low word */
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#define UDC_ADR_CMR_HIGH 0x56 /* channel mode reg, high word */
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#define UDC_ADR_CMR_LOW 0x52 /* channel mode reg, low word */
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#define UDC_ADR_COUNT 0x32 /* number of words to transfer */
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/*
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* For a dma transfer, the appropriate udc registers are loaded from a
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* table in memory pointed to by the chain address register.
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*/
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struct udc_table {
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u_short rsel; /* tells udc which regs to load */
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u_short addrh; /* high word of main mem dma address */
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u_short addrl; /* low word of main mem dma address */
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u_short count; /* num words to transfer */
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u_short cmrh; /* high word of channel mode reg */
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u_short cmrl; /* low word of channel mode reg */
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};
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/* indicates which udc registers are to be set based on info in above table */
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#define UDC_RSEL_RECV 0x0182
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#define UDC_RSEL_SEND 0x0282
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/* setting of chain mode reg: selects how the dma op is to be executed */
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#define UDC_CMR_HIGH 0x0040 /* high word of channel mode reg */
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#define UDC_CMR_LSEND 0x00c2 /* low word of cmr when send */
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#define UDC_CMR_LRECV 0x00d2 /* low word of cmr when receiving */
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/* setting for the master mode register */
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#define UDC_MODE 0xd /* enables udc chip */
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/* setting for the low byte in the high word of an address */
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#define UDC_ADDR_INFO 0x40 /* inc addr after each word is dma'd */
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/* udc commands */
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#define UDC_CMD_STRT_CHN 0xa0 /* start chaining */
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#define UDC_CMD_CIE 0x32 /* channel 1 interrupt enable */
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#define UDC_CMD_RESET 0x00 /* reset udc, same as hdw reset */
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/* bits in the udc status register */
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#define UDC_SR_CIE 0x8000 /* channel interrupt enable */
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#define UDC_SR_IP 0x2000 /* interrupt pending */
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#define UDC_SR_CA 0x1000 /* channel abort */
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#define UDC_SR_NAC 0x0800 /* no auto reload or chaining*/
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#define UDC_SR_WFB 0x0400 /* waiting for bus */
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#define UDC_SR_SIP 0x0200 /* second interrupt pending */
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#define UDC_SR_HM 0x0040 /* hardware mask */
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#define UDC_SR_HRQ 0x0020 /* hardware request */
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#define UDC_SR_MCH 0x0010 /* match on upper comparator byte */
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#define UDC_SR_MCL 0x0008 /* match on lower comparator byte */
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#define UDC_SR_MC 0x0004 /* match condition ended dma */
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#define UDC_SR_EOP 0x0002 /* eop condition ended dma */
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#define UDC_SR_TC 0x0001 /* termination of count ended dma */
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@ -0,0 +1,146 @@
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MI 5380 driver
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==============
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(What? Documentation? Is this guy nuts? :-)
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Reselection
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-----------
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This driver will permit reselection on non-polled commands if
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sc->sc_flags & NCR5380_PERMIT_RESELECT is 1. This permits enabling of
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reselection on a per-device basis.
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Disconnect/reselect is never permitted for polled commands.
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Interfacing the driver to MD code
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---------------------------------
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/sys/dev/ic/ncr5380.c is now stand-alone. DON'T include it after your
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MD stuff!
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This allows for more than one 5380-based SCSI board in your system. This is
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a real possibility for Amiga generic kernels.
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Your driver's softc structure must have an instance of struct ncr5380_softc
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as the first thing in the structure. The MD code must initialize the
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following:
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sci_*: pointers to the 5380 registers. All accesses are done through
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these pointers. This indirection allows the driver to work with
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boards that map the 5380 on even addresses only or do other
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wierdnesses.
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int (*sc_pio_out)(sc, phase, datalen, data)
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int (*sc_pio_in)(sc, phase, datalen, data)
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These point to functions that do programmed I/O transfers to the bus and
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from the bus, respectively. Arguments:
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sc points to the softc
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phase the current SCSI bus phase
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datalen length of data to transfer
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data pointer to the buffer
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Both functions must return the number of bytes successfully transferred.
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A transfer operation must be aborted if the target requests a different
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phase before the transfer completes.
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If you have no special requirements, you can point these to
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ncr5380_pio_out() and ncr5380_pio_in() respectively. If your board
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can do pseudo-DMA, then you might want to point these to functions
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that use this feature.
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void (*sc_dma_alloc)(sc)
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This function is called to set up a DMA transfer. You must create and
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return a "DMA handle" in sc->sc_dma_hand which identifies the DMA transfer.
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The driver will pass you your DMA handle in sc->sc_dma_hand for future
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operations. The contents of the DMA handle are immaterial to the MI
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code - the DMA handle is for your bookkeeping only. Usually, you
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create a structure and point to it here.
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For example, you can record the mapped and unmapped addresses of the
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buffer. The Sun driver places an Am9516 UDC control block in the DMA
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handle.
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If for some reason you decide not to do DMA for the transfer, make
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sc->sc_dma_hand NULL. This might happen if the proposed transfer is
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misaligned, or in the wrong type of memory, or...
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void (*sc_dma_start)(sc)
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This function starts the transfer.
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void (*sc_dma_stop)(sc)
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This function stops a transfer. sc->sc_datalen and sc->sc_dataptr must
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be updated to reflect the portion of the DMA already done.
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void (*sc_dma_eop)(sc)
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This function is called when the 5380 signals EOP. Either continue
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the DMA or stop the DMA.
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void (*sc_dma_free)(sc)
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This function frees the current DMA handle.
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u_char *sc_dataptr;
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int sc_datalen;
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These variables form the active SCSI data pointer. DMA code must start
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DMA at the location given, and update the pointer/length in response to
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DMA operations.
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u_short sc_dma_flags;
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See ncr5380var.h
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Writing your DMA code
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---------------------
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DMA on a system with protected or virtual memory is always a problem. Even
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though a disk transfer may be logically contiguous, the physical pages backing
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the transfer may not be. There are two common solutions to this problem:
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DMA chains: the DMA is broken up into a list of contiguous segments. The first
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segment is submitted to the DMA controller, and when it completes, the second
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segment is submitted, without stopping the 5380. This is what the sc_dma_eop()
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function can do efficiently - if you have a DMA chain, it can quickly load up
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the next link in the chain. The sc_dma_alloc() function builds the chain and
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sc_dma_free() releases any resources you used to build it.
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DVMA: Direct Virtual Memory Access. In this scheme, DMA requests go through
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the MMU. Although you can't page fault, you can program the MMU to remap
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things so the DMA controller sees contiguous data. In this mode, sc_dma_alloc()
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is used to map the transfer into the address space reserved for DVMA and
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sc_dma_free() is used to unmap it.
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Interrupts
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----------
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ncr5380_sbc_intr() must be called when the 5380 interrupts the host.
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You must write an interrupt routine pretty much from scratch to check for
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things generated by MD hardware.
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Known problems
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--------------
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I'm getting this out now so that other ports can hack on it and integrate it.
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The sun3, DMA/Interrupt appears to be working now, but needs testing.
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Polled commands submitted while non-polled commands are in progress are not
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handled correctly. This can happen if reselection is enabled and a new disk
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is mounted while an I/O is in progress on another disk.
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The problem is: what to do if you get reselected while doing the selection
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for the polled command? Currently, the driver busy waits for the non-polled
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command to complete, but this is bogus. I need to complete the non-polled
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command in polled mode, then do the polled command.
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Timeouts in the driver are EXTREMELY sensitive to the characteristics of the
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local implementation of delay(). The Sun3 version delays for a minimum of 5us.
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However, the driver must assume that delay(1) will delay only 1us. For this
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reason, performance on the Sun3 sucks in some places.
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@ -0,0 +1,137 @@
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/* $NetBSD: ncr5380reg.h,v 1.1 1995/10/29 21:19:08 gwr Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* HISTORY (mach3)
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* Revision 2.3 91/08/24 12:25:10 af
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* Moved padding of regmap in impl file.
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* [91/08/02 04:22:39 af]
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*
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* Revision 2.2 91/06/19 16:28:35 rvb
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* From the NCR data sheets
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* "NCR 5380 Family, SCSI Protocol Controller Data Manual"
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* NCR Microelectronics Division, Colorado Spring, 6/98 T01891L
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* [91/04/21 af]
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*
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*/
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/*
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* File: scsi_5380.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 5/91
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*
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* Defines for the NCR 5380 (SCSI chip), aka Am5380
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*/
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/*
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* Register map
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*/
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typedef struct {
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volatile unsigned char sci_data; /* r: Current data */
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#define sci_odata sci_data /* w: Out data */
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volatile unsigned char sci_icmd; /* rw: Initiator command */
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volatile unsigned char sci_mode; /* rw: Mode */
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volatile unsigned char sci_tcmd; /* rw: Target command */
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volatile unsigned char sci_bus_csr; /* r: Bus Status */
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#define sci_sel_enb sci_bus_csr /* w: Select enable */
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volatile unsigned char sci_csr; /* r: Status */
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#define sci_dma_send sci_csr /* w: Start dma send data */
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volatile unsigned char sci_idata; /* r: Input data */
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#define sci_trecv sci_idata /* w: Start dma receive, target */
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volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */
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#define sci_irecv sci_iack /* w: Start dma receive, initiator */
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} sci_regmap_t;
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/*
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* Initiator command register
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*/
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#define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
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#define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
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#define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
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#define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
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#define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
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#define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
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#define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
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#define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
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#define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
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#define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
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/* Bits to keep when doing read/modify/write (leave out RST) */
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#define SCI_ICMD_RMASK 0x1F
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/*
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* Mode register
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*/
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#define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
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#define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
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#define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
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#define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
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#define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
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#define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
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#define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
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#define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */
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/*
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* Target command register
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*/
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#define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
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#define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
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#define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
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#define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
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#define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
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#define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
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* (not on 5380/1) */
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#define SCI_PHASE(x) ((x)&0x7)
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/*
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* Current (SCSI) Bus status (.sci_bus_csr)
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*/
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#define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
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#define SCI_BUS_SEL 0x02 /* r: SEL signal */
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#define SCI_BUS_IO 0x04 /* r: I/O signal */
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#define SCI_BUS_CD 0x08 /* r: C/D signal */
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#define SCI_BUS_MSG 0x10 /* r: MSG signal */
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#define SCI_BUS_REQ 0x20 /* r: REQ signal */
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#define SCI_BUS_BSY 0x40 /* r: BSY signal */
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#define SCI_BUS_RST 0x80 /* r: RST signal */
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#define SCI_CUR_PHASE(x) SCI_PHASE((x)>>2)
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/*
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* Bus and Status register (.sci_csr)
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*/
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#define SCI_CSR_ACK 0x01 /* r: ACK signal */
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#define SCI_CSR_ATN 0x02 /* r: ATN signal */
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#define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
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#define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
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#define SCI_CSR_INT 0x10 /* r: Interrupt request */
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#define SCI_CSR_PERR 0x20 /* r: Parity error */
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#define SCI_CSR_DREQ 0x40 /* r: DMA request */
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#define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,163 @@
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/* $NetBSD: ncr5380var.h,v 1.1 1995/10/29 21:19:10 gwr Exp $ */
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/*
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* Copyright (c) 1995 David Jones, Gordon W. Ross
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* Copyright (c) 1994 Jarle Greipsland
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
|
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* derived from this software without specific prior written permission.
|
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* David Jones and Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file defines the interface between the machine-dependent
|
||||
* module and the machine-indepenedent ncr5380sbc.c module.
|
||||
*/
|
||||
|
||||
#define SCI_CLR_INTR(sc) (*(sc)->sci_iack)
|
||||
#define SCI_BUSY(sc) (*sc->sci_bus_csr & SCI_BUS_BSY)
|
||||
|
||||
#define PHASE_DATA_OUT 0x0
|
||||
#define PHASE_DATA_IN 0x1
|
||||
#define PHASE_CMD 0x2
|
||||
#define PHASE_STATUS 0x3
|
||||
#define PHASE_UNSPEC1 0x4
|
||||
#define PHASE_UNSPEC2 0x5
|
||||
#define PHASE_MSG_OUT 0x6
|
||||
#define PHASE_MSG_IN 0x7
|
||||
|
||||
#define PHASE_INVALID -1
|
||||
|
||||
#define SCSI_PHASE(x) ((x)&0x7)
|
||||
|
||||
/* Per-request state. This is required in order to support reselection. */
|
||||
struct sci_req {
|
||||
struct scsi_xfer *sr_xs; /* Pointer to xfer struct, NULL=unused */
|
||||
int sr_target, sr_lun; /* For fast access */
|
||||
void *sr_dma_hand; /* Current DMA hnadle */
|
||||
u_char *sr_data; /* Saved data pointer */
|
||||
int sr_datalen;
|
||||
int sr_flags; /* Internal error code */
|
||||
#define SR_IMMED 1 /* Immediate command */
|
||||
#define SR_SENSE 2 /* We are getting sense */
|
||||
#define SR_ERROR 4 /* Error occurred */
|
||||
int sr_status; /* Status code from last cmd */
|
||||
};
|
||||
#define SCI_OPENINGS 4 /* Up to 4 commands at once */
|
||||
|
||||
|
||||
struct ncr5380_softc {
|
||||
struct device sc_dev;
|
||||
struct scsi_link sc_link;
|
||||
|
||||
/* Pointers to 5380 registers. MD code must set these up. */
|
||||
volatile u_char *sci_data;
|
||||
volatile u_char *sci_icmd;
|
||||
volatile u_char *sci_mode;
|
||||
volatile u_char *sci_tcmd;
|
||||
volatile u_char *sci_bus_csr;
|
||||
volatile u_char *sci_csr;
|
||||
volatile u_char *sci_idata;
|
||||
volatile u_char *sci_iack;
|
||||
|
||||
/* Functions set from MD code */
|
||||
int (*sc_pio_out) __P((struct ncr5380_softc *,
|
||||
int, int, u_char *));
|
||||
int (*sc_pio_in) __P((struct ncr5380_softc *,
|
||||
int, int, u_char *));
|
||||
void (*sc_dma_alloc) __P((struct ncr5380_softc *));
|
||||
void (*sc_dma_free) __P((struct ncr5380_softc *));
|
||||
void (*sc_dma_start) __P((struct ncr5380_softc *));
|
||||
void (*sc_dma_poll) __P((struct ncr5380_softc *));
|
||||
void (*sc_dma_eop) __P((struct ncr5380_softc *));
|
||||
void (*sc_dma_stop) __P((struct ncr5380_softc *));
|
||||
|
||||
int sc_flags; /* Misc. flags and capabilities */
|
||||
#define NCR5380_PERMIT_RESELECT 1 /* Allow disconnect/reselect */
|
||||
|
||||
int sc_min_dma_len; /* Smaller than this is done with PIO */
|
||||
|
||||
/* Begin MI shared data */
|
||||
|
||||
/* Active data pointer for current SCSI process */
|
||||
u_char *sc_dataptr;
|
||||
int sc_datalen;
|
||||
|
||||
void *sc_dma_hand; /* DMA handle */
|
||||
u_int sc_dma_flags;
|
||||
#define DMA5380_INPROGRESS 1 /* MD: DMA is curently in progress */
|
||||
#define DMA5380_WRITE 2 /* MI: DMA is to output to SCSI */
|
||||
#define DMA5380_POLL 4 /* MI: Poll for DMA completion */
|
||||
#define DMA5380_ERROR 8 /* MD: DMA operation failed */
|
||||
#define DMA5380_PHYS 16 /* MI: Buffer has B_PHYS set */
|
||||
|
||||
/* Begin MI private data */
|
||||
|
||||
/* The request that has the bus now. */
|
||||
struct sci_req *sc_current;
|
||||
|
||||
/* The number of operations in progress on the bus */
|
||||
volatile int sc_ncmds;
|
||||
|
||||
/* Ring buffer of pending/active requests */
|
||||
struct sci_req sc_ring[SCI_OPENINGS];
|
||||
int sc_rr; /* Round-robin scan pointer */
|
||||
|
||||
/* Active requests, by target/LUN */
|
||||
struct sci_req *sc_matrix[8][8];
|
||||
|
||||
/* Message stuff */
|
||||
int sc_prevphase;
|
||||
int sc_msg_flags;
|
||||
#define NCR_DROP_MSGIN 1
|
||||
#define NCR_ABORTING 2
|
||||
#define NCR_NEED_RESET 4
|
||||
u_int sc_msgpriq; /* Messages we want to send */
|
||||
u_int sc_msgoutq; /* Messages sent during last MESSAGE OUT */
|
||||
u_int sc_msgout; /* Message last transmitted */
|
||||
#define SEND_DEV_RESET 0x01
|
||||
#define SEND_PARITY_ERROR 0x02
|
||||
#define SEND_ABORT 0x04
|
||||
#define SEND_REJECT 0x08
|
||||
#define SEND_INIT_DET_ERR 0x10
|
||||
#define SEND_IDENTIFY 0x20
|
||||
#define SEND_SDTR 0x40
|
||||
#define SEND_WDTR 0x80
|
||||
#define NCR_MAX_MSG_LEN 8
|
||||
u_char sc_omess[NCR_MAX_MSG_LEN];
|
||||
u_char *sc_omp; /* Outgoing message pointer */
|
||||
u_char sc_imess[NCR_MAX_MSG_LEN];
|
||||
u_char *sc_imp; /* Incoming message pointer */
|
||||
|
||||
};
|
||||
|
||||
void ncr5380_init __P((struct ncr5380_softc *));
|
||||
void ncr5380_reset_scsibus __P((struct ncr5380_softc *));
|
||||
int ncr5380_sbc_intr __P((struct ncr5380_softc *));
|
||||
int ncr5380_scsi_cmd __P((struct scsi_xfer *));
|
||||
int ncr5380_pio_in __P((struct ncr5380_softc *, int, int, u_char *));
|
||||
int ncr5380_pio_out __P((struct ncr5380_softc *, int, int, u_char *));
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,88 @@
|
|||
/* $NetBSD: ncr_sireg.h,v 1.1 1995/10/29 21:19:12 gwr Exp $ */
|
||||
|
||||
/*
|
||||
* Register map for the Sun3 SCSI Interface (si)
|
||||
* The first part of this register map is an NCR5380
|
||||
* SCSI Bus Interface Controller (SBIC). The rest is a
|
||||
* DMA controller and custom logic in one of two flavors,
|
||||
* one for the OBIO interface (3/50,3/60) and one for the
|
||||
* VME interface (3/160,3/260,etc.), where some registers
|
||||
* are implemented only on one or the other, some on both.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Some of these registers apply to only one interface and some
|
||||
* apply to both. The registers which apply to the Sun3/50 onboard
|
||||
* version only are udc_rdata and udc_raddr. The registers which
|
||||
* apply to the Sun3 vme version only are dma_addr, dma_count, bpr,
|
||||
* iv_am, and bcrh. Thus, the sbc registers, fifo_data, bcr, and csr
|
||||
* apply to both interfaces.
|
||||
* One other feature of the vme interface: a write to the dma count
|
||||
* register also causes a write to the fifo byte count register and
|
||||
* vis versa.
|
||||
*/
|
||||
|
||||
struct si_regs {
|
||||
sci_regmap_t sci; /* See scsi_5380.h */
|
||||
/* DMA controller registers */
|
||||
u_short dma_addrh; /* dma address (VME only) */
|
||||
u_short dma_addrl; /* (high word, low word) */
|
||||
u_short dma_counth; /* dma count (VME only) */
|
||||
u_short dma_countl; /* (high word, low word) */
|
||||
|
||||
/* AMD 9516 regs (OBIO only) see am9516.h */
|
||||
u_short udc_data; /* Am9516, reg data (OBIO only) */
|
||||
u_short udc_addr; /* Am9516, reg addr (OBIO only) */
|
||||
|
||||
/* These three registers are on both OBIO and VME versions. */
|
||||
u_short fifo_data; /* fifo data register */
|
||||
/* holds extra byte on odd */
|
||||
/* byte dma read */
|
||||
u_short fifo_count; /* fifo byte count */
|
||||
u_short si_csr; /* control/status register */
|
||||
|
||||
/* The rest of these are on the VME interface only: */
|
||||
u_short si_bprh; /* byte pack, high (VME only) */
|
||||
u_short si_bprl; /* byte pack, low (VME only) */
|
||||
u_short si_iv_am; /* bits 0-7: intr vector */
|
||||
/* bits 8-13: addr modifier (VME only) */
|
||||
/* bits 14-15: unused */
|
||||
u_short fifo_cnt_hi; /* high part of fifo_count (VME only) */
|
||||
|
||||
/* Whole thing repeats after 32 bytes. */
|
||||
u_short _space[3];
|
||||
};
|
||||
|
||||
/* possible values for the address modifier, sun3 vme version only */
|
||||
#define VME_SUPV_DATA_24 0x3d00
|
||||
|
||||
/*
|
||||
* Status Register.
|
||||
* Note:
|
||||
* (r) indicates bit is read only.
|
||||
* (rw) indicates bit is read or write.
|
||||
* (v) vme host adaptor interface only.
|
||||
* (o) sun3/50 onboard host adaptor interface only.
|
||||
* (b) both vme and sun3/50 host adaptor interfaces.
|
||||
*/
|
||||
#define SI_CSR_DMA_ACTIVE 0x8000 /* (r,o) dma transfer active */
|
||||
#define SI_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while dmaing */
|
||||
#define SI_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during dma */
|
||||
#define SI_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */
|
||||
/* 0 if SCSI-3 unmodified */
|
||||
#define SI_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */
|
||||
#define SI_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */
|
||||
#define SI_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */
|
||||
#define SI_CSR_DMA_IP 0x0100 /* (r,b) dma interrupt pending */
|
||||
#define SI_CSR_LOB 0x00c0 /* (r,v) number of leftover bytes */
|
||||
#define SI_CSR_LOB_THREE 0x00c0 /* (r,v) three leftover bytes */
|
||||
#define SI_CSR_LOB_TWO 0x0080 /* (r,v) two leftover bytes */
|
||||
#define SI_CSR_LOB_ONE 0x0040 /* (r,v) one leftover byte */
|
||||
#define SI_CSR_BPCON 0x0020 /* (rw,v) byte packing control */
|
||||
/* dma is in 0=longwords, 1=words */
|
||||
#define SI_CSR_DMA_EN 0x0010 /* (rw,v) dma enable */
|
||||
#define SI_CSR_SEND 0x0008 /* (rw,b) dma dir, 1=to device */
|
||||
#define SI_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */
|
||||
#define SI_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */
|
||||
#define SI_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */
|
||||
|
||||
Loading…
Reference in New Issue