- reorgazine the entire structure to utilise ifmedia(4)/mii(4) and
redefine starting point of debug. - nuke duplicated standard MII register definition. Davicom PHY extension is defined in dev/mii/dmphyreg.h
This commit is contained in:
nisimura
parent
677813249d
commit
938df3c71a
1336
sys/dev/ic/dm9000.c
1336
sys/dev/ic/dm9000.c
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@ -1,4 +1,4 @@
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/* $NetBSD: dm9000reg.h,v 1.3 2020/03/30 00:01:57 nisimura Exp $ */
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/* $NetBSD: dm9000reg.h,v 1.4 2020/03/31 02:32:25 nisimura Exp $ */
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/*
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* Copyright (c) 2009 Paul Fleischer
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@ -26,17 +26,26 @@
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* SUCH DAMAGE.
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*/
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/* Registers accesible on the DM9000, extracted from pp. 11-12 from the data sheet */
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#ifndef _DEV_IC_DM9000REG_H_
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#define _DEV_IC_DM9000REG_H_
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/* There are two interesting addresses for the DM9000
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* (at least in the context of the FriendlyARM MINI2440)
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* The I/O or register select address, which is the base address.
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* The DATA address, which is located at offset 4 from the base address.
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*
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* Chances are that this will not work generally, as it really depends on how the address lines are
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* mapped from the CPU to the DM9000. But for now it is a good starting point.
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/*
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* Registers accesible on the DM9000, extracted from pp. 11-12 from
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* the data sheet
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*/
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#define DM9000_IOSIZE 4 /* XXX: Depends on the wiring of the address lines. */
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/*
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* There are two interesting addresses for the DM9000 (at least in
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* the context of the FriendlyARM MINI2440) The I/O or register select
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* address, which is the base address. The DATA address, which is
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* located at offset 4 from the base address.
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*
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* Chances are that this will not work generally, as it really depends
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* on how the address lines are mapped from the CPU to the DM9000.
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* But for now it is a good starting point.
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*/
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#define DM9000_IOSIZE 4
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#define DM9000_NCR 0x00
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#define DM9000_NCR_RST (1<<0) /* reset chip, self clear */
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@ -168,38 +177,4 @@
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#define DM9000_IMR_ROOM (1<<3)
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#define DM9000_IMR_PAR (1<<7) /* use 3/13K SRAM w/ auto wrap */
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#define DM9000_PHY_BMCR 0x00
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#define DM9000_PHY_BMCR_COLL_TEST (1<<7)
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#define DM9000_PHY_BMCR_DUPLEX_MODE (1<<8)
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#define DM9000_PHY_BMCR_RESTART_AN (1<<9)
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#define DM9000_PHY_BMCR_ISOLATE (1<<10)
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#define DM9000_PHY_BMCR_POWER_DOWN (1<<11)
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#define DM9000_PHY_BMCR_AUTO_NEG_EN (1<<12)
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#define DM9000_PHY_BMCR_SPEED_SELECT (1<<13)
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#define DM9000_PHY_BMCR_LOOPBACK (1<<14)
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#define DM9000_PHY_BMCR_RESET (1<<15)
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#define DM9000_PHY_BMSR 0x01
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#define DM9000_PHY_BMSR_EXT_CAP (1<<0)
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#define DM9000_PHY_BMSR_JAB_DET (1<<1)
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#define DM9000_PHY_BMSR_LINK_ST (1<<2)
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#define DM9000_PHY_BMSR_AUTO_NEG_AB (1<<3)
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#define DM9000_PHY_BMSR_REMOTE_FAULT (1<<4)
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#define DM9000_PHY_BMSR_AUTO_NEG_COM (1<<5)
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#define DM9000_PHY_BMSR_MF_PRE_SUP (1<<6)
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#define DM9000_PHY_BMSR_10BASE_HALF_DUPLEX (1<<11)
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#define DM9000_PHY_BMSR_10BASE_FULL_DUPLEX (1<<12)
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#define DM9000_PHY_BMSR_100BASE_HALF_DUPLEX (1<<13)
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#define DM9000_PHY_BMSR_100BASE_FULL_DUPLEX (1<<14)
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#define DM9000_PHY_BMSR_100BASE_T4 (1<<15)
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#define DM9000_PHY_PHYID1 0x02
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#define DM9000_PHY_PHYID2 0x03
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#define DM9000_PHY_ANAR 0x04
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#define DM9000_PHY_ANAR_10_HDX (1<<5)
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#define DM9000_PHY_ANAR_10_FDX (1<<6)
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#define DM9000_PHY_ANAR_TX_HDX (1<<7)
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#define DM9000_PHY_ANAR_TX_FDX (1<<8)
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#define DM9000_PHY_ANLPAR 0x05
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#define DM9000_PHY_ANER 0x06
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#define DM9000_PHY_DSCR 0x16 /* Davicom extention */
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#define DM9000_PHY_DSCSR 0x17 /* Davicom extention */
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#define DM9000_PHY_10BTCSR 0x18 /* Davicom extention */
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: dm9000var.h,v 1.5 2020/03/05 15:18:55 riastradh Exp $ */
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/* $NetBSD: dm9000var.h,v 1.6 2020/03/31 02:32:25 nisimura Exp $ */
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/*
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* Copyright (c) 2009 Paul Fleischer
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@ -64,6 +64,7 @@
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#define _DEV_IC_DM9000VAR_H_
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#include <sys/callout.h>
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#include <sys/rndsource.h>
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#define DM9000_MODE_8BIT 2
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#define DM9000_MODE_16BIT 0
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@ -71,13 +72,8 @@
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struct dme_softc {
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device_t sc_dev; /* Generic Base Device */
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struct ethercom sc_ethercom; /* Ethernet common data */
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struct ifmedia sc_media; /* Media control structures */
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uint sc_media_active;
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uint sc_media_status;
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struct mii_data sc_mii; /* MII/media information */
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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void *sc_ih;
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for transmission. */
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uint16_t txready_length;
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int (*sc_pkt_write)(struct dme_softc*, struct mbuf *);
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int (*sc_pkt_read)(struct dme_softc*, struct ifnet *, struct mbuf **);
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int (*sc_pkt_write)(struct dme_softc *, struct mbuf *);
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int (*sc_pkt_read)(struct dme_softc *, struct mbuf **);
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callout_t sc_link_callout;
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@ -107,6 +103,7 @@ struct dme_softc {
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#ifdef DIAGNOSTIC
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bool sc_inside_interrupt;
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#endif
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krndsource_t rnd_source;
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};
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/* Function declarations */
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@ -114,9 +111,6 @@ int dme_attach(struct dme_softc *, const uint8_t *);
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int dme_detach(struct dme_softc *);
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int dme_intr(void *);
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/* Helper method used by sc_pkt_read */
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struct mbuf* dme_alloc_receive_buffer(struct ifnet *, unsigned int);
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/* Inline memory access methods */
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static __inline uint8_t
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dme_read(struct dme_softc *sc, int reg)
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@ -140,7 +134,7 @@ dme_write2(struct dme_softc *sc, int reg, uint16_t value)
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}
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static __inline void
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dme_write_c(struct dme_softc *sc, int reg, uint8_t value[], uint count)
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dme_write_c(struct dme_softc *sc, int reg, const uint8_t value[], uint count)
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{
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for(int i=0; i<count; i++) {
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dme_write(sc, reg+i, value[i]);
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}
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#endif /* _DEV_IC_DM9000VAR_H_ */
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