a minor bit of cleanup
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ecd1b40ab3
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92995a3a9f
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@ -1,4 +1,4 @@
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/* $NetBSD: dwlpx_pci.c,v 1.6 1997/04/07 23:40:34 cgd Exp $ */
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/* $NetBSD: dwlpx_pci.c,v 1.7 1997/08/16 01:16:33 mjacob Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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@ -33,7 +33,7 @@
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#include <machine/options.h> /* Config options headers */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.6 1997/04/07 23:40:34 cgd Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.7 1997/08/16 01:16:33 mjacob Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -47,8 +47,6 @@ __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.6 1997/04/07 23:40:34 cgd Exp $");
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#include <alpha/pci/dwlpxreg.h>
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#include <alpha/pci/dwlpxvar.h>
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#define DO_SECONDARIES 1
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#define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
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void dwlpx_attach_hook __P((struct device *, struct device *,
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@ -149,7 +147,6 @@ dwlpx_conf_read(cpv, tag, offset)
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sc = ccp->cc_sc;
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secondary = tag >> 24;
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if (secondary) {
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#ifdef DO_SECONDARIES
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tag &= 0x1fffff;
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tag |= (secondary << 21);
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@ -164,14 +161,12 @@ dwlpx_conf_read(cpv, tag, offset)
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* Set up HPCs for type 1 cycles.
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*/
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 1;
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
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PCIA_CTL_T1CYC;
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alpha_mb();
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REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
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alpha_mb();
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}
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#else
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return (data);
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#endif
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}
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paddr = (unsigned long) tag;
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paddr |= DWLPX_PCI_CONF;
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@ -188,16 +183,15 @@ dwlpx_conf_read(cpv, tag, offset)
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if (secondary) {
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alpha_pal_draina();
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & ~1;
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
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~PCIA_CTL_T1CYC;
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alpha_mb();
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REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
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alpha_mb();
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}
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(void) splx(s);
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#ifdef DO_SECONDARIES
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#if 0
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printf("=%x\n", data);
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#endif
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#endif
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}
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return (data);
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@ -236,7 +230,8 @@ dwlpx_conf_write(cpv, tag, offset, data)
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* Set up HPCs for type 1 cycles.
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*/
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 1;
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
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PCIA_CTL_T1CYC;
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alpha_mb();
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REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
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alpha_mb();
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@ -256,7 +251,8 @@ dwlpx_conf_write(cpv, tag, offset, data)
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if (secondary) {
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alpha_pal_draina();
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for (i = 0; i < sc->dwlpx_nhpc; i++) {
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & ~1;
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rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
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~PCIA_CTL_T1CYC;
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alpha_mb();
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REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
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alpha_mb();
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