Add SRMMU/sun4m definitions.
Cleanup (i.e. mostly delete) `#if defined (SUN4*)' in here.
This commit is contained in:
pk
parent
e86e25ba54
commit
922201e06a
@ -1,6 +1,8 @@
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/* $NetBSD: ctlreg.h,v 1.9 1995/10/23 23:36:28 pk Exp $ */
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/* $NetBSD: ctlreg.h,v 1.10 1996/03/31 22:06:58 pk Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard University. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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@ -10,6 +12,7 @@
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University.
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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@ -45,95 +48,87 @@
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*/
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/*
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* Sun-4, 4c, and 4m control registers. (includes address space definitions
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* Sun4M support by Aaron Brown, Harvard University.
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* Changes Copyright (c) 1995 The President and Fellows of Harvard College.
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* All rights reserved.
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*
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* $Id: ctlreg.h,v 1.10 1996/03/31 22:06:58 pk Exp $
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*/
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/*
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* Sun 4, 4c, and 4m control registers. (includes address space definitions
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* and some registers in control space).
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*/
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/*
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* The Alternate address spaces.
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*/
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/* 0x00 unused */
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/* 0x01 unused */
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#if defined(SUN4C) || defined(SUN4)
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#define ASI_CONTROL 0x02 /* cache enable, context reg, etc */
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#define ASI_SEGMAP 0x03 /* segment maps (so we can reach each pmeg) */
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#define ASI_PTE 0x04 /* PTE space (pmegs) */
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#define ASI_REGMAP 0x06 /* region maps (3 level MMUs only) */
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#define ASI_HWFLUSHSEG 0x05 /* hardware assisted version of FLUSHSEG */
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#define ASI_HWFLUSHPG 0x06 /* hardware assisted version of FLUSHPG */
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#define ASI_HWFLUSHCTX 0x07 /* hardware assisted version of FLUSHCTX */
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#endif
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#if defined(SUN4M)
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#define ASI_SRMMUFP 0x03 /* ref mmu flush/probe */
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#define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */
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#define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/
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#define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */
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#define ASI_SRMMU 0x04 /* ref mmu registers */
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#define ASI_SRMMUDIAG 0x06
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#endif
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#define ASI_SEGMAP 0x03 /* [4/4c] segment maps */
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#define ASI_SRMMUFP 0x03 /* [4m] ref mmu flush/probe */
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#define ASI_PTE 0x04 /* [4/4c] PTE space (pmegs) */
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#define ASI_SRMMU 0x04 /* [4m] ref mmu registers */
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#define ASI_REGMAP 0x06 /* [4/3-level MMU ] region maps */
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#define ASI_HWFLUSHSEG 0x05 /* [4/4c] hardware assisted version of FLUSHSEG */
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#define ASI_HWFLUSHPG 0x06 /* [4/4c] hardware assisted version of FLUSHPG */
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#define ASI_SRMMUDIAG 0x06 /* [4m] */
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#define ASI_HWFLUSHCTX 0x07 /* [4/4c] hardware assisted version of FLUSHCTX */
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#define ASI_USERI 0x08 /* I-space (user) */
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#define ASI_KERNELI 0x09 /* I-space (kernel) */
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#define ASI_USERD 0x0a /* D-space (user) */
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#define ASI_KERNELD 0x0b /* D-space (kernel) */
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#if defined(SUN4C) || defined(SUN4)
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#define ASI_FLUSHREG 0x7 /* causes hardware to flush cache region */
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#define ASI_FLUSHSEG 0x0c /* causes hardware to flush cache segment */
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#define ASI_FLUSHPG 0x0d /* causes hardware to flush cache page */
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#define ASI_FLUSHCTX 0x0e /* causes hardware to flush cache context */
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#endif
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#if defined(SUN4)
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#define ASI_DCACHE 0x0f /* flush data cache; not used on 4c */
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#endif
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#define ASI_FLUSHREG 0x7 /* [4/4c] flush cache by region */
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#define ASI_FLUSHSEG 0x0c /* [4/4c] flush cache by segment */
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#define ASI_FLUSHPG 0x0d /* [4/4c] flush cache by page */
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#define ASI_FLUSHCTX 0x0e /* [4/4c] flush cache by context */
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#if defined(SUN4M)
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#define ASI_ICACHETAG 0x0c /* instruction cache tag */
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#define ASI_ICACHEDATA 0x0d /* instruction cache data */
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#define ASI_DCACHETAG 0x0e /* data cache tag */
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#define ASI_DCACHEDATA 0x0f /* data cache data */
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#define ASI_IDCACHELFP 0x10 /* ms2 only: flush i&d cache line (page) */
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#define ASI_IDCACHELFS 0x11 /* ms2 only: flush i&d cache line (seg) */
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#define ASI_IDCACHELFR 0x12 /* ms2 only: flush i&d cache line (reg) */
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#define ASI_IDCACHELFC 0x13 /* ms2 only: flush i&d cache line (ctxt) */
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#define ASI_IDCACHELFU 0x14 /* ms2 only: flush i&d cache line (user) */
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#define ASI_BYPASS 0x20 /* sun ref mmu bypass, ie. direct phys access */
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#define ASI_ICACHECLR 0x36 /* ms1 only: instruction cache flash clear */
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#define ASI_DCACHECLR 0x37 /* ms1 only: data cache clear */
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#define ASI_DCACHEDIAG 0x39 /* data cache diagnostic register access */
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#endif
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#define ASI_DCACHE 0x0f /* [4] flush data cache */
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#if defined(SUN4C) || defined(SUN4)
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/* registers in the control space */
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#define AC_CONTEXT 0x30000000 /* context register (byte) */
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#define AC_SYSENABLE 0x40000000 /* system enable register (byte) */
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#define AC_CACHETAGS 0x80000000 /* cache tag base address */
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#define AC_SERIAL 0xf0000000 /* special serial port sneakiness */
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#define ASI_ICACHETAG 0x0c /* [4m] instruction cache tag */
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#define ASI_ICACHEDATA 0x0d /* [4m] instruction cache data */
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#define ASI_DCACHETAG 0x0e /* [4m] data cache tag */
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#define ASI_DCACHEDATA 0x0f /* [4m] data cache data */
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#define ASI_IDCACHELFP 0x10 /* [4m] ms2 only: flush i&d cache line (page) */
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#define ASI_IDCACHELFS 0x11 /* [4m] ms2 only: flush i&d cache line (seg) */
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#define ASI_IDCACHELFR 0x12 /* [4m] ms2 only: flush i&d cache line (reg) */
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#define ASI_IDCACHELFC 0x13 /* [4m] ms2 only: flush i&d cache line (ctxt) */
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#define ASI_IDCACHELFU 0x14 /* [4m] ms2 only: flush i&d cache line (user) */
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#define ASI_BYPASS 0x20 /* [4m] sun ref mmu bypass,
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ie. direct phys access */
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#define ASI_ICACHECLR 0x36 /* [4m] ms1 only: I-cache flash clear */
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#define ASI_DCACHECLR 0x37 /* [4m] ms1 only: D-cache flash clear */
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#define ASI_DCACHEDIAG 0x39 /* [4m] data cache diagnostic register access */
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/*
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* [4/4c] Registers in the control space (ASI_CONTROL).
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*/
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#define AC_IDPROM 0x00000000 /* [4] ID PROM */
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#define AC_CONTEXT 0x30000000 /* [4/4c] context register (byte) */
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#define AC_SYSENABLE 0x40000000 /* [4/4c] system enable register (byte) */
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#define AC_DVMA_ENABLE 0x50000000 /* [4] enable user dvma */
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#define AC_BUS_ERR 0x60000000 /* [4] bus error register */
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#define AC_SYNC_ERR 0x60000000 /* [4c] sync (memory) error reg */
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#define AC_SYNC_VA 0x60000004 /* [4c] sync error virtual addr */
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#define AC_ASYNC_ERR 0x60000008 /* [4c] async error reg */
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#define AC_ASYNC_VA 0x6000000c /* [4c] async error virtual addr */
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#define AC_DIAG_REG 0x70000000 /* [4] diagnostic reg */
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#define AC_CACHETAGS 0x80000000 /* [4/4c?] cache tag base address */
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#define AC_CACHEDATA 0x90000000 /* [4] cached data [sun4/400?] */
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#define AC_DVMA_MAP 0xd0000000 /* [4] user dvma map entries */
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#define AC_VMEINTVEC 0xe0000000 /* [4] vme interrupt vector */
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#define AC_SERIAL 0xf0000000 /* [4/4c] special serial port sneakiness */
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/* AC_SERIAL is not used in the kernel (it is for the PROM) */
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#endif
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#if defined(SUN4)
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#define AC_IDPROM 0x00000000 /* ID PROM */
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#define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */
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#define AC_BUS_ERR 0x60000000 /* bus error register */
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#define AC_DIAG_REG 0x70000000 /* diagnostic reg */
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#define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */
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#define AC_VMEINTVEC 0xe0000000 /* vme interrupt vector */
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/* XXX: does not belong here */
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#define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */
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#endif
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#if defined(SUN4C)
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#define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */
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#define AC_SYNC_VA 0x60000004 /* sync error virtual addr */
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#define AC_ASYNC_ERR 0x60000008 /* async error reg */
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#define AC_ASYNC_VA 0x6000000c /* async error virtual addr */
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#define AC_CACHEDATA 0x90000000 /* cached data */
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#endif
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#if defined(SUN4C) || defined(SUN4)
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/*
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* [4/4c]
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* Bits in sync error register. Reading the register clears these;
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* otherwise they accumulate. The error(s) occurred at the virtual
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* address stored in the sync error address register, and may have
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@ -147,13 +142,14 @@
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#define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */
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#define SER_SBUSERR 0x10 /* S-Bus bus error */
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#define SER_MEMERR 0x08 /* memory ecc/parity error */
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#define SER_SZERR 0x02 /* size error, whatever that is */
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#define SER_SZERR 0x02 /* [4/vme?] size error, whatever that is */
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#define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */
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#define SER_BITS \
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"\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG"
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/*
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* [4/4c]
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* Bits in async error register (errors from DVMA or Sun-4 cache
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* writeback). The corresponding bit is also set in the sync error reg.
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*
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@ -168,7 +164,7 @@
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#define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR"
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/*
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* Bits in system enable register.
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* [4/4c] Bits in system enable register.
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*/
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#define SYSEN_DVMA 0x20 /* Enable dvma */
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#define SYSEN_CACHE 0x10 /* Enable cache */
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@ -176,19 +172,74 @@
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#define SYSEN_VIDEO 0x08 /* Enable on-board video */
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#define SYSEN_RESET 0x04 /* Reset the hardware */
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#define SYSEN_RESETVME 0x02 /* Reset the VME bus */
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#endif
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#if defined(SUN4M)
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/*
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* [4m] Bits in ASI_CONTROL? space, sun4m only.
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*/
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#define MXCC_ENABLE_ADDR 0x1c00a00 /* Enable register for MXCC */
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#define MXCC_ENABLE_BIT 0x4 /* Enable bit for MXCC */
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/*
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* Bits in ASI_SRMMUFP space.
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* Bits 8-11 determine the type of flush/probe.
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* Address bits 12-31 hold the page frame.
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*/
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#define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */
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#define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/
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#define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */
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/*
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* [4m] Registers and bits in the SPARC Reference MMU (ASI_SRMMU).
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*/
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#define SRMMU_PCR 0x00000000 /* Processor control register */
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#define SRMMU_CXTPTR 0x00000100 /* Context table pointer register */
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#define SRMMU_CXR 0x00000200 /* Context register */
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#define SRMMU_SFSTAT 0x00000300 /* Synchronous fault status reg */
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#define SRMMU_SFADDR 0x00000400 /* Synchronous fault address reg */
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#define SRMMU_AFSTAT 0x00000500 /* Asynchronous fault status reg (HS) */
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#define SRMMU_AFADDR 0x00000600 /* Asynchronous fault address reg (HS)*/
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#define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */
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/* Synchronous Fault Status Register bits */
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/* [4m] Bits in SRMMU control register */
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#define SRMMU_PCR_ME 0x00000001 /* MMU Enable */
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#define SRMMU_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define SRMMU_PCR_PSO 0x00000080 /* Partial Store Ordering enable */
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#define SRMMU_PCR_CE 0x00000100 /* HS: Cache enable bit (HyperSPARC) */
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#define SRMMU_PCR_DCE 0x00000100 /* SS: Data cache enable bit */
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#define SRMMU_PCR_ICE 0x00000200 /* SS: SuperSPARC instr. cache enable */
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#define SRMMU_PCR_CM 0x00000400 /* HS: Cache mode: 1 == write-back */
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#define SRMMU_PCR_SB 0x00000400 /* SS: Store buffer enable bit */
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#define SRMMU_PCR_MR 0x00000800 /* HS: Memory reflection: 1 == on */
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#define SRMMU_PCR_MB 0x00000800 /* SS: MBus mode: 0=MXCC, 1=no MXCC */
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#define SRMMU_PCR_CS 0x00001000 /* HS: cache size: 1==256k, 0==128k */
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#define SRMMU_PCR_PE 0x00001000 /* SS: Enable memory parity checking */
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#define SRMMU_PCR_C 0x00002000 /* HS: enable cache when MMU off */
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#define SRMMU_PCR_SSBM 0x00002000 /* SS: 1 iff booting */
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#define SRMMU_PCR_HSBM 0x00004000 /* HS: 1 iff booting */
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#define SRMMU_PCR_SSSE 0x00004000 /* SS: Coherent bus snoop enable */
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#define SRMMU_PCR_AC 0x00008000 /* SS: 1=cache non-MMU accesses */
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#define SRMMU_PCR_TC 0x00010000 /* SS: 1=cache table walks */
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#define SRMMU_PCR_MID 0x00078000 /* HS: MBus module ID MID<3:0> */
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#define SRMMU_PCR_WBE 0x00080000 /* HS: Write buffer enable */
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#define SRMMU_PCR_HSSE 0x00100000 /* HS: Coherent bus snoop enable */
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#define SRMMU_PCR_CWR 0x00200000 /* HS: Cache wrap enable */
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#define SRMMU_PCR_VER 0x0f000000 /* Version of MMU implementation */
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#define SRMMU_PCR_IMPL 0xf0000000 /* Implementation number of MMU */
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#ifdef notyet
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#define SRMMU_PCR_INITIAL (SRMMU_PCR_ME | SRMMU_PCR_TC)
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#endif
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/* [4m] Bits in the Synchronous Fault Status Register */
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#define SFSR_EM 0x00020000 /* Error mode watchdog reset occurred */
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#define SFSR_CS 0x00010000 /* Control Space error */
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#define SFSR_PERR 0x00006000 /* Parity error code */
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#define SFSR_SB 0x00008000 /* SS: Store Buffer Error */
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#define SFSR_P 0x00004000 /* SS: Parity error */
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#define SFSR_UC 0x00001000 /* Uncorrectable error */
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#define SFSR_TO 0x00000800 /* S-Bus timeout */
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#define SFSR_BE 0x00000400 /* S-Bus bus error */
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#define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */
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@ -197,7 +248,50 @@
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#define SFSR_FAV 0x00000002 /* Fault Address is valid */
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#define SFSR_OW 0x00000001 /* Overwritten with new fault */
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/* TLB Replacement Control Register bits */
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#define SFSR_BITS \
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"\20\21CSERR\17PARITY\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\2FAV\1OW"
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/* [4m] Synchronous Fault Types */
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#define SFSR_FT_NONE (0 << 2) /* no fault */
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#define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */
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#define SFSR_FT_PROTERR (2 << 2) /* protection fault */
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#define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */
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#define SFSR_FT_TRANSERR (4 << 2) /* translation fault */
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#define SFSR_FT_BUSERR (5 << 2) /* access bus error */
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#define SFSR_FT_INTERR (6 << 2) /* internal error */
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#define SFSR_FT_RESERVED (7 << 2) /* reserved */
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/* [4m] Synchronous Fault Access Types */
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#define SFSR_AT_LDUDATA (0 << 5) /* Load user data */
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#define SFSR_AT_LDSDATA (1 << 5) /* Load supervisor data */
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#define SFSR_AT_LDUTEXT (2 << 5) /* Load user text */
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#define SFSR_AT_LDSTEXT (3 << 5) /* Load supervisor text */
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#define SFSR_AT_STUDATA (4 << 5) /* Store user data */
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#define SFSR_AT_STSDATA (5 << 5) /* Store supervisor data */
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#define SFSR_AT_STUTEXT (6 << 5) /* Store user text */
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#define SFSR_AT_STSTEXT (7 << 5) /* Store supervisor text */
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#define SFSR_AT_SUPERVISOR (1 << 5) /* Set iff supervisor */
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#define SFSR_AT_TEXT (2 << 5) /* Set iff text */
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#define SFSR_AT_STORE (4 << 5) /* Set iff store */
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/* [4m] Synchronous Fault PT Levels */
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#define SFSR_LVL_0 (0 << 8) /* Context table entry */
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#define SFSR_LVL_1 (1 << 8) /* Region table entry */
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#define SFSR_LVL_2 (2 << 8) /* Segment table entry */
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#define SFSR_LVL_3 (3 << 8) /* Page table entry */
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/* [4m] Asynchronous Fault Status Register bits */
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#define AFSR_AFO 0x00000001 /* Async. fault occurred */
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#define AFSR_AFA 0x000000f0 /* Bits <35:32> of faulting phys addr */
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#define AFSR_AFA_RSHIFT 4 /* Shift to get AFA to bit 0 */
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#define AFSR_AFA_LSHIFT 28 /* Shift to get AFA to bit 32 */
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#define AFSR_BE 0x00000400 /* Bus error */
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#define AFSR_TO 0x00000800 /* Bus timeout */
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#define AFSR_UC 0x00001000 /* Uncorrectable error */
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#define AFSR_SE 0x00002000 /* System error */
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#define AFSR_BITS "\20\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\1AFO"
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/* [4m] TLB Replacement Control Register bits */
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#define TLBC_DISABLE 0x00000020 /* Disable replacement counter */
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#define TLBC_RCNTMASK 0x0000001f /* Replacement counter (0-31) */
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#endif
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@ -1,6 +1,8 @@
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/* $NetBSD: pte.h,v 1.14 1996/03/14 19:49:16 christos Exp $ */
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/* $NetBSD: pte.h,v 1.15 1996/03/31 22:06:55 pk Exp $ */
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||||
|
||||
/*
|
||||
* Copyright (c) 1996
|
||||
* The President and Fellows of Harvard University. All rights reserved.
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
@ -9,7 +11,8 @@
|
||||
* contributed to Berkeley.
|
||||
*
|
||||
* All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* must display the following acknowledgements:
|
||||
* This product includes software developed by Harvard University.
|
||||
* This product includes software developed by the University of
|
||||
* California, Lawrence Berkeley Laboratory.
|
||||
*
|
||||
@ -22,7 +25,8 @@
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* must display the following acknowledgements:
|
||||
* This product includes software developed by Harvard University.
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
@ -42,11 +46,13 @@
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)pte.h 8.1 (Berkeley) 6/11/93
|
||||
*
|
||||
* $Id: pte.h,v 1.15 1996/03/31 22:06:55 pk Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
* Sun-4 (sort of) and 4c (SparcStation) Page Table Entries
|
||||
* (Sun call them `Page Map Entries').
|
||||
* Sun-4 (sort of), 4c (SparcStation), and 4m Page Table Entries
|
||||
* (Sun calls them `Page Map Entries').
|
||||
*/
|
||||
|
||||
#ifndef _LOCORE
|
||||
@ -83,6 +89,17 @@ typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */
|
||||
* (for sun4)
|
||||
* 3. take the value from (2 or 3) above and concatenate va<17:13> to
|
||||
* get a `page map entry' index. This gives a 32-bit PTE.
|
||||
**
|
||||
* For sun4m:
|
||||
* 1. Use context_reg<3:0> to index the context table (located at
|
||||
* (context_reg << 2) | ((ctx_tbl_ptr_reg >> 2) << 6) ). This
|
||||
* gives a 32-bit page-table-descriptor (PTP).
|
||||
* 2. Use va<31:24> to index the region table located by the PTP from (1):
|
||||
* PTP<31:6> << 10. This gives another PTP for the segment tables
|
||||
* 3. Use va<23:18> to index the segment table located by the PTP from (2)
|
||||
* as follows: PTP<31:4> << 8. This gives another PTP for the page tbl.
|
||||
* 4. Use va<17:12> to index the page table given by (3)'s PTP:
|
||||
* PTP<31:4> << 8. This gives a 32-bit PTE.
|
||||
*
|
||||
* In other words:
|
||||
*
|
||||
@ -105,14 +122,46 @@ typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */
|
||||
* va_off:12; (offset within page)
|
||||
* };
|
||||
*
|
||||
* struct sun4m_virtual_addr {
|
||||
* u_int va_reg:8, (virtual region)
|
||||
* va_seg:6, (virtual segment within region)
|
||||
* va_pg:6, (virtual page within segment)
|
||||
* va_off:12; (offset within page)
|
||||
* };
|
||||
*
|
||||
* Then, given any `va':
|
||||
*
|
||||
* extern smeg_t regmap[16][1<<8]; (3-level MMU only)
|
||||
* extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4)
|
||||
* extern int ptetable[128][1<<6]; ([512][1<<5] for sun4)
|
||||
*
|
||||
* (the above being in the hardware, accessed as Alternate Address Spaces)
|
||||
* extern u_int s4m_ctxmap[16]; (sun4m SRMMU only)
|
||||
* extern u_int s4m_regmap[16][1<<8]; (sun4m SRMMU only)
|
||||
* extern u_int s4m_segmap[1<<8][1<<6]; (sun4m SRMMU only)
|
||||
* extern u_int s4m_pagmap[1<<14][1<<6]; (sun4m SRMMU only)
|
||||
*
|
||||
* (the above being in the hardware, accessed as Alternate Address Spaces on
|
||||
* all machines but the Sun4m SRMMU, in which case the tables are in physical
|
||||
* kernel memory. In the 4m architecture, the tables are not layed out as
|
||||
* 2-dim arrays, but are sparsely allocated as needed, and point to each
|
||||
* other.)
|
||||
*
|
||||
* if (cputyp==CPU_SUN4M) // SPARC Reference MMU
|
||||
* regptp = s4m_ctxmap[curr_ctx];
|
||||
* if (!(regptp & SRMMU_TEPTD)) TRAP();
|
||||
* segptp = *(u_int *)(((regptp & ~0x3) << 4) | va.va_reg);
|
||||
* if (!(segptp & SRMMU_TEPTD)) TRAP();
|
||||
* pagptp = *(u_int *)(((segptp & ~0x3) << 4) | va.va_seg);
|
||||
* if (!(pagptp & SRMMU_TEPTD)) TRAP();
|
||||
* pte = *(u_int *)(((pagptp & ~0x3) << 4) | va.va_pg);
|
||||
* if (!(pte & SRMMU_TEPTE)) TRAP(); // like PG_V
|
||||
* if (usermode && PTE_PROT_LEVEL(pte) > 0x5) TRAP();
|
||||
* if (writing && !PTE_PROT_LEVEL_ALLOWS_WRITING(pte)) TRAP();
|
||||
* if (!(pte & SRMMU_PG_C)) DO_NOT_USE_CACHE_FOR_THIS_ACCESS();
|
||||
* pte |= SRMMU_PG_U;
|
||||
* if (writing) pte |= PG_M;
|
||||
* physaddr = ((pte & SRMMU_PG_PFNUM) << SRMMU_PGSHIFT)|va.va_off;
|
||||
* return;
|
||||
* if (mmu_3l)
|
||||
* physreg = regmap[curr_ctx][va.va_reg];
|
||||
* physseg = segmap[physreg][va.va_seg];
|
||||
@ -147,7 +196,7 @@ extern int mmu_3l;
|
||||
#define SGOFSET (NBPSG - 1) /* mask for segment offset */
|
||||
|
||||
/* number of PTEs that map one segment (not number that fit in one segment!) */
|
||||
#if defined(SUN4) && defined(SUN4C)
|
||||
#if defined(SUN4) && (defined(SUN4C) || defined(SUN4M))
|
||||
extern int nptesg;
|
||||
#define NPTESG nptesg /* (which someone will have to initialize) */
|
||||
#else
|
||||
@ -163,6 +212,12 @@ extern int nptesg;
|
||||
/* virtual address to virtual page number, for Sun-4 and Sun-4c */
|
||||
#define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31)
|
||||
#define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63)
|
||||
#define VA_SUN4M_VPG(va) (((int)(va) >> 12) & 63)
|
||||
|
||||
/* virtual address to offset within page */
|
||||
#define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF)
|
||||
#define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF)
|
||||
#define VA_SUN4M_OFF(va) (((int)(va)) & 0xFFF)
|
||||
|
||||
/* truncate virtual address to region base */
|
||||
#define VA_ROUNDDOWNTOREG(va) ((int)(va) & ~RGOFSET)
|
||||
@ -171,16 +226,29 @@ extern int nptesg;
|
||||
#define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET)
|
||||
|
||||
/* virtual segment to virtual address (must sign extend on holy MMUs!) */
|
||||
#if defined(MMU_3L)
|
||||
#define VRTOVA(vr) (mmu_3l \
|
||||
#if defined(SUN4M) && !(defined(SUN4C) || defined(SUN4))
|
||||
#define VRTOVA(vr) ((int)(vr) << RGSHIFT)
|
||||
#define VSTOVA(vr,vs) (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT))
|
||||
#else
|
||||
#if defined(MMU_3L) || defined(SUN4M) /* hairy.. */
|
||||
#if !defined(MMU_3L)
|
||||
#define _PTE_HAIRY_3L_TEST (cputyp==CPU_SUN4M)
|
||||
#elif !defined(SUN4M)
|
||||
#define _PTE_HAIRY_3L_TEST (mmu_3l)
|
||||
#else
|
||||
#define _PTE_HAIRY_3L_TEST (mmu_3l || cputyp==CPU_SUN4M)
|
||||
#endif
|
||||
#define VRTOVA(vr) (_PTE_HAIRY_3L_TEST \
|
||||
? ((int)(vr) << RGSHIFT) \
|
||||
: (((int)(vr) << (RGSHIFT+2)) >> 2))
|
||||
#define VSTOVA(vr,vs) (mmu_3l \
|
||||
? (((int)vr << RGSHIFT) + ((int)(vs) << SGSHIFT)) \
|
||||
: ((((int)vr << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT)))
|
||||
#define VSTOVA(vr,vs) (_PTE_HAIRY_3L_TEST \
|
||||
? (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT)) \
|
||||
: ((((int)(vr) << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT)))
|
||||
#else
|
||||
#define VRTOVA(vr) (((int)(vr) << (RGSHIFT+2)) >> 2)
|
||||
#define VSTOVA(vr,vs) ((((int)(vr) << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT))
|
||||
#define VSTOVA(vr,vs) ((((int)(vr) << (RGSHIFT+2)) >> 2) + \
|
||||
((int)(vs) << SGSHIFT))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern int mmu_has_hole;
|
||||
@ -192,17 +260,30 @@ extern int mmu_has_hole;
|
||||
#define MMU_HOLE_START 0x20000000
|
||||
#define MMU_HOLE_END 0xe0000000
|
||||
|
||||
#if defined(SUN4M) /* Optimization: sun4m, sun4c have same page */
|
||||
#if defined(SUN4) /* size, so they're used interchangeably */
|
||||
#define VA_VPG(va) (cputyp==CPU_SUN4 ? VA_SUN4_VPG(va) : VA_SUN4C_VPG(va))
|
||||
#define VA_OFF(VA) (cputyp==CPU_SUN4 ? VA_SUN4_OFF(va) : VA_SUN4C_OFF(va))
|
||||
#else
|
||||
#define VA_VPG(va) VA_SUN4M_VPG(va)
|
||||
#define VA_OFF(va) VA_SUN4M_OFF(va)
|
||||
#endif /* defined SUN4 */
|
||||
#else /* 4m not defined */
|
||||
#if defined(SUN4) && defined(SUN4C)
|
||||
#define VA_VPG(va) (cputyp==CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va))
|
||||
#define VA_OFF(va) (cputyp==CPU_SUN4C ? VA_SUN4C_OFF(va) : VA_SUN4_OFF(va))
|
||||
#endif
|
||||
#if defined(SUN4C) && !defined(SUN4)
|
||||
#define VA_VPG(va) VA_SUN4C_VPG(va)
|
||||
#define VA_OFF(va) VA_SUN4C_OFF(va)
|
||||
#endif
|
||||
#if !defined(SUN4C) && defined(SUN4)
|
||||
#define VA_VPG(va) VA_SUN4_VPG(va)
|
||||
#define VA_OFF(va) VA_SUN4_OFF(va)
|
||||
#endif
|
||||
#endif /* defined 4m */
|
||||
|
||||
/* there is no `struct pte'; we just use `int' */
|
||||
/* there is no `struct pte'; we just use `int'; this is for non-4M only */
|
||||
#define PG_V 0x80000000
|
||||
#define PG_PROT 0x60000000 /* both protection bits */
|
||||
#define PG_W 0x40000000 /* allowed to write */
|
||||
@ -212,20 +293,23 @@ extern int mmu_has_hole;
|
||||
|
||||
#define PG_OBMEM 0x00000000 /* on board memory */
|
||||
#define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */
|
||||
#ifdef SUN4
|
||||
#define PG_VME16 0x08000000 /* 16-bit-data VME space */
|
||||
#define PG_VME32 0x0c000000 /* 32-bit-data VME space */
|
||||
#if defined(SUN4M)
|
||||
#define PG_SUN4M_OBMEM 0x0 /* No type bits=>obmem on 4m */
|
||||
#define PG_SUN4M_OBIO 0xf /* obio maps to 0xf on 4M */
|
||||
#define SRMMU_PGTYPE 0xf0000000 /* Top 4 bits of pte PPN give type */
|
||||
#endif
|
||||
|
||||
#define PG_U 0x02000000
|
||||
#define PG_M 0x01000000
|
||||
#define PG_IOC 0x00800000 /* IO-cacheable */
|
||||
#define PG_IOC 0x00800000
|
||||
#define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */
|
||||
#define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */
|
||||
|
||||
#define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */
|
||||
#define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */
|
||||
|
||||
#define PG_M_SHIFT4M 5 /* shift to get SRMMU_PG_M,R on 4m */
|
||||
/*efine PG_NOACC 0 ** XXX */
|
||||
#define PG_KR 0x20000000
|
||||
#define PG_KW 0x60000000
|
||||
@ -245,6 +329,18 @@ struct pte {
|
||||
pg_mbz:5,
|
||||
pg_pfnum:19;
|
||||
};
|
||||
#if defined(SUN4M)
|
||||
struct srmmu_pte {
|
||||
u_int pg_pfnum:20,
|
||||
pg_c:1,
|
||||
pg_m:1,
|
||||
pg_u:1;
|
||||
enum pgprot { pprot_r_r, pprot_rw_rw, pprot_rx_rx, pprot_rwx_rwx,
|
||||
pprot_x_x, pprot_r_rw, pprot_n_rx, pprot_n_rwx }
|
||||
pg_prot:3; /* prot. bits: pprot_<user>_<supervisor> */
|
||||
u_int pg_must_be_2:2;
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -258,48 +354,61 @@ struct pte {
|
||||
#define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */
|
||||
#define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */
|
||||
|
||||
/* %%%: Fix above and below for 4m? */
|
||||
|
||||
/* static __inline int PG_VALID(void *va) {
|
||||
register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1);
|
||||
} */
|
||||
|
||||
#if defined(SUN4M)
|
||||
|
||||
/*
|
||||
* Reference MMU PTE bits.
|
||||
* Here are the bit definitions for 4M/SRMMU pte's
|
||||
*/
|
||||
#define SRPTE_PPN_MASK 0x07ffff00
|
||||
#define SRPTE_PPN_SHIFT 8
|
||||
#define SRPTE_CACHEABLE 0x00000080 /* Page is cacheable */
|
||||
#define SRPTE_MOD 0x00000040 /* Page is modified */
|
||||
#define SRPTE_REF 0x00000020 /* Page is referenced */
|
||||
#define SRPTE_ACCMASK 0x0000001c /* Access rights mask */
|
||||
#define SRPTE_ACCSHIFT 2 /* Access rights shift */
|
||||
#define SRPTE_TYPEMASK 0x00000003 /* PTE Type */
|
||||
#define SRPTE_PTE 0x00000002 /* A PTE (Page Table Entry) */
|
||||
#define SRPTE_PTP 0x00000001 /* A PTP (Page Table Pointer) */
|
||||
|
||||
/*
|
||||
* Reference MMU access permission bits.
|
||||
* format: SRACC_sssuuu,
|
||||
* where <sss> denote the supervisor rights
|
||||
* and <uuu> denote the user rights
|
||||
*/
|
||||
#define SRACC_R__R__ 0
|
||||
#define SRACC_RW_RW_ 1
|
||||
#define SRACC_R_XR_X 2
|
||||
#define SRACC_RWXRWX 3
|
||||
#define SRACC___X__X 4
|
||||
#define SRACC_RW_R__ 5
|
||||
#define SRACC_R_X___ 6
|
||||
#define SRACC_RWX___ 7
|
||||
/* MMU TABLE ENTRIES */
|
||||
#define SRMMU_TEINVALID 0x0 /* invalid (serves as !valid bit) */
|
||||
#define SRMMU_TEPTD 0x1 /* Page Table Descriptor */
|
||||
#define SRMMU_TEPTE 0x2 /* Page Table Entry */
|
||||
#define SRMMU_TERES 0x3 /* reserved */
|
||||
#define SRMMU_TETYPE 0x3 /* mask for table entry type */
|
||||
/* PTE FIELDS */
|
||||
#define SRMMU_PPNMASK 0xFFFFFF00
|
||||
#define SRMMU_PPNSHIFT 0x8
|
||||
#define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */
|
||||
#define SRMMU_L1PPNSHFT 0x14
|
||||
#define SRMMU_L1PPNMASK 0xFFF00000
|
||||
#define SRMMU_L2PPNSHFT 0xE
|
||||
#define SRMMU_L2PPNMASK 0xFC000
|
||||
#define SRMMU_L3PPNSHFT 0x8
|
||||
#define SRMMU_L3PPNMASK 0x3F00
|
||||
/* PTE BITS */
|
||||
#define SRMMU_PG_C 0x80 /* cacheable */
|
||||
#define SRMMU_PG_M 0x40 /* modified (dirty) */
|
||||
#define SRMMU_PG_R 0x20 /* referenced */
|
||||
#define SRMMU_PGBITSMSK 0xE0
|
||||
/* PTE PROTECTION */
|
||||
#define SRMMU_PROT_MASK 0x1C /* Mask protection bits out of pte */
|
||||
#define SRMMU_PROT_SHFT 0x2
|
||||
#define PPROT_R_R 0x0 /* These are in the form: */
|
||||
#define PPROT_RW_RW 0x4 /* PPROT_<u>_<s> */
|
||||
#define PPROT_RX_RX 0x8 /* where <u> is the user-mode */
|
||||
#define PPROT_RWX_RWX 0xC /* permission, and <s> is the */
|
||||
#define PPROT_X_X 0x10 /* supervisor mode permission. */
|
||||
#define PPROT_R_RW 0x14 /* R=read, W=write, X=execute */
|
||||
#define PPROT_N_RX 0x18 /* N=none. */
|
||||
#define PPROT_N_RWX 0x1C
|
||||
#define PPROT_WRITE 0x4 /* set iff write priv. allowed */
|
||||
#define PPROT_S 0x18 /* effective S bit */
|
||||
#define PPROT_U2S_OMASK 0x18 /* OR with prot. to revoke user priv */
|
||||
/* TABLE SIZES */
|
||||
#define SRMMU_L1SIZE 0x100
|
||||
#define SRMMU_L2SIZE 0x40
|
||||
#define SRMMU_L3SIZE 0x40
|
||||
|
||||
/*
|
||||
* IOMMU PTE bits.
|
||||
*/
|
||||
#define IOPTE_PPN_MASK 0x07ffff00
|
||||
#define IOPTE_PPN_SHIFT 8
|
||||
#define IOPTE_RSVD 0x000000f1
|
||||
#define IOPTE_WRITE 0x00000004
|
||||
#define IOPTE_VALID 0x00000002
|
||||
|
||||
#endif /* SUN4M */
|
||||
#define IOPTE_PPN_MASK 0x07ffff00
|
||||
#define IOPTE_PPN_SHIFT 8
|
||||
#define IOPTE_RSVD 0x000000f1
|
||||
#define IOPTE_WRITE 0x00000004
|
||||
#define IOPTE_VALID 0x00000002
|
||||
|
||||
Loading…
Reference in New Issue
Block a user