Split the ahcisata driver in pci front-end and bus-independant back-end.
This commit is contained in:
bouyer
parent
a9a3224a5e
commit
920d7a6afe
@ -1,4 +1,4 @@
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# $NetBSD: files,v 1.843 2007/05/08 16:48:37 xtraeme Exp $
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# $NetBSD: files,v 1.844 2007/05/12 11:04:58 bouyer Exp $
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# @(#)files.newconf 7.5 (Berkeley) 5/10/93
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@ -891,6 +891,11 @@ file dev/ic/wdc_upc.c wdc_upc
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file dev/ic/com_upc.c com_upc
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file dev/ic/lpt_upc.c lpt_upc
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# AHCI-compatible SATA controllers
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define ahcisata_core
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file dev/ic/ahcisata_core.c ahcisata_core
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device ahcisata: ata, ata_dma, ata_udma, sata, ahcisata_core
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# DECchip 21x4x Ethernet controller family, and assorted clones.
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#
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device tlp: arp, ether, ifnet, mii, mii_bitbang
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@ -1,4 +1,4 @@
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/* $NetBSD: ahcisata.c,v 1.4 2007/03/04 06:02:16 christos Exp $ */
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/* $NetBSD: ahcisata_core.c,v 1.1 2007/05/12 11:04:58 bouyer Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ahcisata.c,v 1.4 2007/03/04 06:02:16 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.1 2007/05/12 11:04:58 bouyer Exp $");
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#include <sys/types.h>
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#include <sys/malloc.h>
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@ -42,79 +42,16 @@ __KERNEL_RCSID(0, "$NetBSD: ahcisata.c,v 1.4 2007/03/04 06:02:16 christos Exp $"
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#include <uvm/uvm_extern.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/ahcisatareg.h>
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#include <dev/ic/wdcreg.h>
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#include <dev/ata/atareg.h>
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#include <dev/ata/satavar.h>
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#include <dev/ata/satareg.h>
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#include <dev/ic/ahcisatavar.h>
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#define AHCI_DEBUG
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#define DEBUG_INTR 0x01
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#define DEBUG_XFERS 0x02
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#define DEBUG_FUNCS 0x08
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#define DEBUG_PROBE 0x10
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#define DEBUG_DETACH 0x20
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#ifdef AHCI_DEBUG
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int ahcidebug_mask = 0x0;
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#define AHCIDEBUG_PRINT(args, level) \
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if (ahcidebug_mask & (level)) \
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printf args
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#else
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#define AHCIDEBUG_PRINT(args, level)
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#endif
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struct ahci_softc {
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struct atac_softc sc_atac;
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bus_space_tag_t sc_ahcit; /* ahci registers mapping */
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bus_space_handle_t sc_ahcih;
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bus_dma_tag_t sc_dmat; /* DMA memory mappings: */
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void *sc_cmd_hdr; /* command tables and received FIS */
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bus_dmamap_t sc_cmd_hdrd;
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int sc_ncmds; /* number of command slots */
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struct ata_channel *sc_chanarray[AHCI_MAX_PORTS];
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struct ahci_channel {
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struct ata_channel ata_channel; /* generic part */
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bus_space_handle_t ahcic_scontrol;
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bus_space_handle_t ahcic_sstatus;
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bus_space_handle_t ahcic_serror;
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/* pointers allocated from sc_cmd_hdrd */
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struct ahci_r_fis *ahcic_rfis; /* received FIS */
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bus_addr_t ahcic_bus_rfis;
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struct ahci_cmd_header *ahcic_cmdh; /* command headers */
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bus_addr_t ahcic_bus_cmdh;
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/* command tables (allocated per-channel) */
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bus_dmamap_t ahcic_cmd_tbld;
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struct ahci_cmd_tbl *ahcic_cmd_tbl[AHCI_MAX_CMDS];
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bus_addr_t ahcic_bus_cmd_tbl[AHCI_MAX_CMDS];
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bus_dmamap_t ahcic_datad[AHCI_MAX_CMDS];
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u_int32_t ahcic_cmds_active; /* active commands */
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} sc_channels[AHCI_MAX_PORTS];
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};
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#define AHCINAME(sc) ((sc)->sc_atac.atac_dev.dv_xname)
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#define AHCI_CMDH_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
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(sc)->sc_cmd_hdrd, \
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(char *)(&(achp)->ahcic_cmdh[(cmd)]) - (char *)(sc)->sc_cmd_hdr, \
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sizeof(struct ahci_cmd_header), (op))
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#define AHCI_RFIS_SYNC(sc, achp, op) bus_dmamap_sync((sc)->sc_dmat, \
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(sc)->sc_cmd_hdrd, (void *)(achp)->ahcic_rfis - (sc)->sc_cmd_hdr, \
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AHCI_RFIS_SIZE, (op))
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#define AHCI_CMDTBL_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
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(achp)->ahcic_cmd_tbld, AHCI_CMDTBL_SIZE * (cmd), \
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AHCI_CMDTBL_SIZE, (op))
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#define AHCI_READ(sc, reg) bus_space_read_4((sc)->sc_ahcit, \
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(sc)->sc_ahcih, (reg))
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#define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \
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(sc)->sc_ahcih, (reg), (val))
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void ahci_probe_drive(struct ata_channel *);
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void ahci_setup_channel(struct ata_channel *);
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@ -151,49 +88,11 @@ const struct ata_bustype ahci_ata_bustype = {
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ahci_killpending
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};
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static int ahci_match(struct device *, struct cfdata *, void *);
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static void ahci_attach(struct device *, struct device *, void *);
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int ahci_intr(void *);
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void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
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CFATTACH_DECL(ahcisata, sizeof(struct ahci_softc),
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ahci_match, ahci_attach, NULL, NULL);
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static int
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ahci_match(struct device *parent, struct cfdata *match,
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void *aux)
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void
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ahci_attach(struct ahci_softc *sc)
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{
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struct pci_attach_args *pa = aux;
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bus_space_tag_t regt;
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bus_space_handle_t regh;
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bus_size_t size;
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int ret = 0;
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
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PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) {
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/* check if the chip is in ahci mode */
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if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
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®t, ®h, NULL, &size) != 0)
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return (0);
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if (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE)
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ret = 3;
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bus_space_unmap(regt, regh, size);
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return (3);
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}
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return (ret);
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}
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static void
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ahci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct ahci_softc *sc = (struct ahci_softc *)self;
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bus_size_t size;
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char devinfo[256];
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u_int32_t ahci_cap, ahci_rev, ahci_ports;
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int i, j, port;
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struct ahci_channel *achp;
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@ -204,16 +103,7 @@ ahci_attach(struct device *parent, struct device *self, void *aux)
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int dmasize;
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void *cmdhp;
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void *cmdtblp;
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const char *intrstr;
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pci_intr_handle_t intrhandle;
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void *ih;
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if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) {
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aprint_error("%s: can't map ahci registers\n", AHCINAME(sc));
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return;
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}
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/* reset controller */
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AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
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delay(1000);
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@ -233,9 +123,6 @@ ahci_attach(struct device *parent, struct device *self, void *aux)
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ahci_cap = AHCI_READ(sc, AHCI_CAP);
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sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1;
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sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
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aprint_naive(": AHCI disk controller\n");
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aprint_normal(": %s\n", devinfo);
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ahci_rev = AHCI_READ(sc, AHCI_VS);
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aprint_normal("%s: AHCI revision ", AHCINAME(sc));
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switch(ahci_rev) {
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@ -263,7 +150,6 @@ ahci_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
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sc->sc_atac.atac_set_modes = ahci_setup_channel;
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sc->sc_dmat = pa->pa_dmat;
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dmasize =
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(AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
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error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
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@ -298,18 +184,6 @@ ahci_attach(struct device *parent, struct device *self, void *aux)
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/* clear interrupts */
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AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
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if (pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc));
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc);
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if (ih == NULL) {
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aprint_error("%s: couldn't establish interrupt", AHCINAME(sc));
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return;
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}
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aprint_normal("%s: interrupting at %s\n", AHCINAME(sc),
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intrstr ? intrstr : "unknown interrupt");
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/* enable interrupts */
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AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
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@ -1,4 +1,4 @@
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/* $NetBSD: ahcisatareg.h,v 1.1 2006/11/30 21:01:16 bouyer Exp $ */
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/* $NetBSD: ahcisatareg.h,v 1.1 2007/05/12 11:04:58 bouyer Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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101
sys/dev/ic/ahcisatavar.h
Normal file
101
sys/dev/ic/ahcisatavar.h
Normal file
@ -0,0 +1,101 @@
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/* $NetBSD: ahcisatavar.h,v 1.1 2007/05/12 11:04:58 bouyer Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <dev/ic/ahcisatareg.h>
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#define AHCI_DEBUG
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#define DEBUG_INTR 0x01
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#define DEBUG_XFERS 0x02
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#define DEBUG_FUNCS 0x08
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#define DEBUG_PROBE 0x10
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#define DEBUG_DETACH 0x20
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#ifdef AHCI_DEBUG
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extern int ahcidebug_mask;
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#define AHCIDEBUG_PRINT(args, level) \
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if (ahcidebug_mask & (level)) \
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printf args
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#else
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#define AHCIDEBUG_PRINT(args, level)
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#endif
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struct ahci_softc {
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struct atac_softc sc_atac;
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bus_space_tag_t sc_ahcit; /* ahci registers mapping */
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bus_space_handle_t sc_ahcih;
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bus_dma_tag_t sc_dmat; /* DMA memory mappings: */
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void *sc_cmd_hdr; /* command tables and received FIS */
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bus_dmamap_t sc_cmd_hdrd;
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int sc_ncmds; /* number of command slots */
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struct ata_channel *sc_chanarray[AHCI_MAX_PORTS];
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struct ahci_channel {
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struct ata_channel ata_channel; /* generic part */
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bus_space_handle_t ahcic_scontrol;
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bus_space_handle_t ahcic_sstatus;
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bus_space_handle_t ahcic_serror;
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/* pointers allocated from sc_cmd_hdrd */
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struct ahci_r_fis *ahcic_rfis; /* received FIS */
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bus_addr_t ahcic_bus_rfis;
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struct ahci_cmd_header *ahcic_cmdh; /* command headers */
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bus_addr_t ahcic_bus_cmdh;
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/* command tables (allocated per-channel) */
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bus_dmamap_t ahcic_cmd_tbld;
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struct ahci_cmd_tbl *ahcic_cmd_tbl[AHCI_MAX_CMDS];
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bus_addr_t ahcic_bus_cmd_tbl[AHCI_MAX_CMDS];
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bus_dmamap_t ahcic_datad[AHCI_MAX_CMDS];
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u_int32_t ahcic_cmds_active; /* active commands */
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} sc_channels[AHCI_MAX_PORTS];
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};
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#define AHCINAME(sc) ((sc)->sc_atac.atac_dev.dv_xname)
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#define AHCI_CMDH_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
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(sc)->sc_cmd_hdrd, \
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(char *)(&(achp)->ahcic_cmdh[(cmd)]) - (char *)(sc)->sc_cmd_hdr, \
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sizeof(struct ahci_cmd_header), (op))
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#define AHCI_RFIS_SYNC(sc, achp, op) bus_dmamap_sync((sc)->sc_dmat, \
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(sc)->sc_cmd_hdrd, (void *)(achp)->ahcic_rfis - (sc)->sc_cmd_hdr, \
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AHCI_RFIS_SIZE, (op))
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#define AHCI_CMDTBL_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
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(achp)->ahcic_cmd_tbld, AHCI_CMDTBL_SIZE * (cmd), \
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AHCI_CMDTBL_SIZE, (op))
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#define AHCI_READ(sc, reg) bus_space_read_4((sc)->sc_ahcit, \
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(sc)->sc_ahcih, (reg))
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#define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \
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(sc)->sc_ahcih, (reg), (val))
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void ahci_attach(struct ahci_softc *);
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int ahci_intr(void *);
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119
sys/dev/pci/ahcisata_pci.c
Normal file
119
sys/dev/pci/ahcisata_pci.c
Normal file
@ -0,0 +1,119 @@
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/* $NetBSD: ahcisata_pci.c,v 1.1 2007/05/12 11:04:59 bouyer Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
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* This product includes software developed by Manuel Bouyer.
|
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* 4. The name of the author may not be used to endorse or promote products
|
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* derived from this software without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.1 2007/05/12 11:04:59 bouyer Exp $");
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/disklabel.h>
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#include <uvm/uvm_extern.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
|
||||
#include <dev/ic/ahcisatavar.h>
|
||||
|
||||
static int ahci_pci_match(struct device *, struct cfdata *, void *);
|
||||
static void ahci_pci_attach(struct device *, struct device *, void *);
|
||||
|
||||
CFATTACH_DECL(ahcisata_pci, sizeof(struct ahci_softc),
|
||||
ahci_pci_match, ahci_pci_attach, NULL, NULL);
|
||||
|
||||
static int
|
||||
ahci_pci_match(struct device *parent, struct cfdata *match,
|
||||
void *aux)
|
||||
{
|
||||
struct pci_attach_args *pa = aux;
|
||||
bus_space_tag_t regt;
|
||||
bus_space_handle_t regh;
|
||||
bus_size_t size;
|
||||
int ret = 0;
|
||||
|
||||
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
|
||||
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
|
||||
PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) {
|
||||
/* check if the chip is in ahci mode */
|
||||
if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
|
||||
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
|
||||
®t, ®h, NULL, &size) != 0)
|
||||
return (0);
|
||||
if (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE)
|
||||
ret = 3;
|
||||
bus_space_unmap(regt, regh, size);
|
||||
return (3);
|
||||
}
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static void
|
||||
ahci_pci_attach(struct device *parent, struct device *self, void *aux)
|
||||
{
|
||||
struct pci_attach_args *pa = aux;
|
||||
struct ahci_softc *sc = (struct ahci_softc *)self;
|
||||
bus_size_t size;
|
||||
char devinfo[256];
|
||||
const char *intrstr;
|
||||
pci_intr_handle_t intrhandle;
|
||||
void *ih;
|
||||
|
||||
if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
|
||||
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
|
||||
&sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) {
|
||||
aprint_error("%s: can't map ahci registers\n", AHCINAME(sc));
|
||||
return;
|
||||
}
|
||||
pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
|
||||
aprint_naive(": AHCI disk controller\n");
|
||||
aprint_normal(": %s\n", devinfo);
|
||||
|
||||
if (pci_intr_map(pa, &intrhandle) != 0) {
|
||||
aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc));
|
||||
return;
|
||||
}
|
||||
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
|
||||
ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc);
|
||||
if (ih == NULL) {
|
||||
aprint_error("%s: couldn't establish interrupt", AHCINAME(sc));
|
||||
return;
|
||||
}
|
||||
aprint_normal("%s: interrupting at %s\n", AHCINAME(sc),
|
||||
intrstr ? intrstr : "unknown interrupt");
|
||||
sc->sc_dmat = pa->pa_dmat;
|
||||
ahci_attach(sc);
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: files.pci,v 1.286 2007/04/26 19:47:03 garbled Exp $
|
||||
# $NetBSD: files.pci,v 1.287 2007/05/12 11:04:59 bouyer Exp $
|
||||
#
|
||||
# Config file and device description for machine-independent PCI code.
|
||||
# Included by ports that need it. Requires that the SCSI files be
|
||||
@ -217,9 +217,8 @@ attach pciide at pci
|
||||
file dev/pci/pciide.c pciide
|
||||
|
||||
# AHCI SATA controllers
|
||||
device ahcisata: ata, ata_dma, ata_udma, sata
|
||||
attach ahcisata at pci
|
||||
file dev/pci/ahcisata.c ahcisata
|
||||
attach ahcisata at pci with ahcisata_pci
|
||||
file dev/pci/ahcisata_pci.c ahcisata_pci
|
||||
|
||||
# Acard IDE controllers
|
||||
device acardide: ata, ata_dma, ata_udma, pciide_common, wdc_common
|
||||
|
||||
Loading…
Reference in New Issue
Block a user