ep93xx processor VIC interrupt controller support
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joff
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5fd3b99d04
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540
sys/arch/arm/ep93xx/ep93xx_intr.c
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540
sys/arch/arm/ep93xx/ep93xx_intr.c
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/* $NetBSD: ep93xx_intr.c,v 1.1 2004/12/22 19:07:14 joff Exp $ */
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/*
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jesse Off
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ichiro FUKUHARA and Naoto Shimazaki.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ep93xx_intr.c,v 1.1 2004/12/22 19:07:14 joff Exp $");
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/*
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* Interrupt support for the Cirrus Logic EP93XX
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/termios.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/ep93xx/ep93xxreg.h>
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#include <arm/ep93xx/ep93xxvar.h>
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/* Interrupt handler queues. */
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struct intrq intrq[NIRQ];
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/* Interrupts to mask at each level. */
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static u_int32_t vic1_imask[NIPL];
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static u_int32_t vic2_imask[NIPL];
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/* Current interrupt priority level. */
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__volatile int current_spl_level;
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__volatile int hardware_spl_level;
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/* Software copy of the IRQs we have enabled. */
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__volatile u_int32_t vic1_intr_enabled;
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__volatile u_int32_t vic2_intr_enabled;
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/* Interrupts pending. */
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static __volatile int ipending;
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/*
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* Map a software interrupt queue index (to the unused bits in the
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* VIC1 register -- XXX will need to revisit this if those bits are
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* ever used in future steppings).
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*/
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static const u_int32_t si_to_irqbit[SI_NQUEUES] = {
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EP93XX_INTR_bit30, /* SI_SOFT */
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EP93XX_INTR_bit29, /* SI_SOFTCLOCK */
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EP93XX_INTR_bit28, /* SI_SOFTNET */
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EP93XX_INTR_bit27, /* SI_SOFTSERIAL */
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};
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#define INT_SWMASK \
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((1U << EP93XX_INTR_bit30) | (1U << EP93XX_INTR_bit29) | \
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(1U << EP93XX_INTR_bit28) | (1U << EP93XX_INTR_bit27))
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#define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)])
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/*
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* Map a software interrupt queue to an interrupt priority level.
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*/
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static const int si_to_ipl[SI_NQUEUES] = {
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IPL_SOFT, /* SI_SOFT */
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IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
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IPL_SOFTNET, /* SI_SOFTNET */
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IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
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};
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void ep93xx_intr_dispatch(struct irqframe *frame);
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#define VIC1REG(reg) *((volatile u_int32_t*) (EP93XX_AHB_VBASE + \
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EP93XX_AHB_VIC1 + (reg)))
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#define VIC2REG(reg) *((volatile u_int32_t*) (EP93XX_AHB_VBASE + \
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EP93XX_AHB_VIC2 + (reg)))
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static void
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ep93xx_set_intrmask(u_int32_t vic1_irqs, u_int32_t vic2_irqs)
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{
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VIC1REG(EP93XX_VIC_IntEnClear) = vic1_irqs;
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VIC1REG(EP93XX_VIC_IntEnable) = vic1_intr_enabled & ~vic1_irqs;
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VIC2REG(EP93XX_VIC_IntEnClear) = vic2_irqs;
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VIC2REG(EP93XX_VIC_IntEnable) = vic2_intr_enabled & ~vic2_irqs;
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}
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static void
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ep93xx_enable_irq(int irq)
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{
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if (irq < VIC_NIRQ) {
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vic1_intr_enabled |= (1U << irq);
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VIC1REG(EP93XX_VIC_IntEnable) = (1U << irq);
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} else {
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vic2_intr_enabled |= (1U << (irq - VIC_NIRQ));
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VIC2REG(EP93XX_VIC_IntEnable) = (1U << (irq - VIC_NIRQ));
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}
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}
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static __inline void
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ep93xx_disable_irq(int irq)
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{
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if (irq < VIC_NIRQ) {
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vic1_intr_enabled &= ~(1U << irq);
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VIC1REG(EP93XX_VIC_IntEnClear) = (1U << irq);
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} else {
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vic2_intr_enabled &= ~(1U << (irq - VIC_NIRQ));
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VIC2REG(EP93XX_VIC_IntEnClear) = (1U << (irq - VIC_NIRQ));
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}
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}
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/*
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* NOTE: This routine must be called with interrupts disabled in the CPSR.
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*/
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static void
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ep93xx_intr_calculate_masks(void)
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{
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struct intrq *iq;
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struct intrhand *ih;
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int irq, ipl;
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/* First, figure out which IPLs each IRQ has. */
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for (irq = 0; irq < NIRQ; irq++) {
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int levels = 0;
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iq = &intrq[irq];
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ep93xx_disable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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levels |= (1U << ih->ih_ipl);
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iq->iq_levels = levels;
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}
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/* Next, figure out which IRQs are used by each IPL. */
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for (ipl = 0; ipl < NIPL; ipl++) {
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int vic1_irqs = 0;
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int vic2_irqs = 0;
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for (irq = 0; irq < VIC_NIRQ; irq++) {
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if (intrq[irq].iq_levels & (1U << ipl))
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vic1_irqs |= (1U << irq);
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}
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vic1_imask[ipl] = vic1_irqs;
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for (irq = 0; irq < VIC_NIRQ; irq++) {
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if (intrq[irq + VIC_NIRQ].iq_levels & (1U << ipl))
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vic2_irqs |= (1U << irq);
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}
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vic2_imask[ipl] = vic2_irqs;
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}
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vic1_imask[IPL_NONE] = 0;
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vic2_imask[IPL_NONE] = 0;
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/*
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* Initialize the soft interrupt masks to block themselves.
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*/
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vic1_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
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vic1_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
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vic1_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
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vic1_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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/*
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* splsoftclock() is the only interface that users of the
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* generic software interrupt facility have to block their
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* soft intrs, so splsoftclock() must also block IPL_SOFT.
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*/
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vic1_imask[IPL_SOFTCLOCK] |= vic1_imask[IPL_SOFT];
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vic2_imask[IPL_SOFTCLOCK] |= vic2_imask[IPL_SOFT];
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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vic1_imask[IPL_SOFTNET] |= vic1_imask[IPL_SOFTCLOCK];
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vic2_imask[IPL_SOFTNET] |= vic2_imask[IPL_SOFTCLOCK];
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/*
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* Enforce a heirarchy that gives "slow" device (or devices with
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* limited input buffer space/"real-time" requirements) a better
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* chance at not dropping data.
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*/
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vic1_imask[IPL_BIO] |= vic1_imask[IPL_SOFTNET];
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vic2_imask[IPL_BIO] |= vic2_imask[IPL_SOFTNET];
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vic1_imask[IPL_NET] |= vic1_imask[IPL_BIO];
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vic2_imask[IPL_NET] |= vic2_imask[IPL_BIO];
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vic1_imask[IPL_SOFTSERIAL] |= vic1_imask[IPL_NET];
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vic2_imask[IPL_SOFTSERIAL] |= vic2_imask[IPL_NET];
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vic1_imask[IPL_TTY] |= vic1_imask[IPL_SOFTSERIAL];
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vic2_imask[IPL_TTY] |= vic2_imask[IPL_SOFTSERIAL];
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/*
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* splvm() blocks all interrupts that use the kernel memory
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* allocation facilities.
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*/
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vic1_imask[IPL_VM] |= vic1_imask[IPL_TTY];
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vic2_imask[IPL_VM] |= vic2_imask[IPL_TTY];
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/*
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* Audio devices are not allowed to perform memory allocation
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* in their interrupt routines, and they have fairly "real-time"
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* requirements, so give them a high interrupt priority.
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*/
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vic1_imask[IPL_AUDIO] |= vic1_imask[IPL_VM];
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vic2_imask[IPL_AUDIO] |= vic2_imask[IPL_VM];
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/*
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* splclock() must block anything that uses the scheduler.
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*/
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vic1_imask[IPL_CLOCK] |= vic1_imask[IPL_AUDIO];
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vic2_imask[IPL_CLOCK] |= vic2_imask[IPL_AUDIO];
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/*
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* No separate statclock on the EP93xx.
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*/
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vic1_imask[IPL_STATCLOCK] |= vic1_imask[IPL_CLOCK];
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vic2_imask[IPL_STATCLOCK] |= vic2_imask[IPL_CLOCK];
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/*
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* serial uarts have small buffers that need low-latency servicing
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*/
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vic1_imask[IPL_SERIAL] |= vic1_imask[IPL_STATCLOCK];
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vic2_imask[IPL_SERIAL] |= vic2_imask[IPL_STATCLOCK];
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/*
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* splhigh() must block "everything".
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*/
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vic1_imask[IPL_HIGH] |= vic1_imask[IPL_SERIAL];
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vic2_imask[IPL_HIGH] |= vic2_imask[IPL_SERIAL];
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/*
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* Now compute which IRQs must be blocked when servicing any
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* given IRQ.
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*/
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for (irq = 0; irq < NIRQ; irq++) {
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int vic1_irqs;
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int vic2_irqs;
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if (irq < VIC_NIRQ) {
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vic1_irqs = (1U << irq);
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vic2_irqs = 0;
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} else {
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vic1_irqs = 0;
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vic2_irqs = (1U << (irq - VIC_NIRQ));
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}
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iq = &intrq[irq];
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if (TAILQ_FIRST(&iq->iq_list) != NULL)
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ep93xx_enable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list)) {
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vic1_irqs |= vic1_imask[ih->ih_ipl];
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vic2_irqs |= vic2_imask[ih->ih_ipl];
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}
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iq->iq_vic1_mask = vic1_irqs;
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iq->iq_vic2_mask = vic2_irqs;
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}
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}
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static void
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ep93xx_do_pending(void)
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{
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static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
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int new;
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u_int oldirqstate;
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if (__cpu_simple_lock_try(&processing) == 0)
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return;
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new = current_spl_level;
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oldirqstate = disable_interrupts(I32_bit);
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#define DO_SOFTINT(si) \
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if ((ipending & ~vic1_imask[new]) & SI_TO_IRQBIT(si)) { \
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ipending &= ~SI_TO_IRQBIT(si); \
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current_spl_level = si_to_ipl[(si)]; \
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restore_interrupts(oldirqstate); \
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softintr_dispatch(si); \
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oldirqstate = disable_interrupts(I32_bit); \
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current_spl_level = new; \
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}
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DO_SOFTINT(SI_SOFTSERIAL);
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DO_SOFTINT(SI_SOFTNET);
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DO_SOFTINT(SI_SOFTCLOCK);
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DO_SOFTINT(SI_SOFT);
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__cpu_simple_unlock(&processing);
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restore_interrupts(oldirqstate);
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}
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__inline void
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splx(int new)
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{
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int old;
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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old = current_spl_level;
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current_spl_level = new;
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if (new != hardware_spl_level) {
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hardware_spl_level = new;
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ep93xx_set_intrmask(vic1_imask[new], vic2_imask[new]);
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}
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restore_interrupts(oldirqstate);
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/* If there are software interrupts to process, do it. */
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if ((ipending & INT_SWMASK) & ~vic1_imask[new])
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ep93xx_do_pending();
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}
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int
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_splraise(int ipl)
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{
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int old;
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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old = current_spl_level;
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current_spl_level = ipl;
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restore_interrupts(oldirqstate);
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return (old);
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}
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int
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_spllower(int ipl)
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{
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int old = current_spl_level;
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if (old <= ipl)
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return (old);
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splx(ipl);
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return (old);
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}
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void
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_setsoftintr(int si)
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{
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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ipending |= SI_TO_IRQBIT(si);
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restore_interrupts(oldirqstate);
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/* Process unmasked pending soft interrupts. */
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if ((ipending & INT_SWMASK) & ~vic1_imask[current_spl_level])
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ep93xx_do_pending();
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}
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/*
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* ep93xx_intr_init:
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*
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* Initialize the rest of the interrupt subsystem, making it
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* ready to handle interrupts from devices.
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*/
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void
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ep93xx_intr_init(void)
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{
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struct intrq *iq;
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int i;
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vic1_intr_enabled = 0;
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vic2_intr_enabled = 0;
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for (i = 0; i < NIRQ; i++) {
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iq = &intrq[i];
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TAILQ_INIT(&iq->iq_list);
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sprintf(iq->iq_name, "irq %d", i);
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evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
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NULL, (i < VIC_NIRQ ? "vic1" : "vic2"),
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iq->iq_name);
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}
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current_intr_depth = 0;
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current_spl_level = 0;
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hardware_spl_level = 0;
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/* All interrupts should use IRQ not FIQ */
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VIC1REG(EP93XX_VIC_IntSelect) = 0;
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VIC2REG(EP93XX_VIC_IntSelect) = 0;
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ep93xx_intr_calculate_masks();
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/* Enable IRQs (don't yet use FIQs). */
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enable_interrupts(I32_bit);
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}
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void *
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ep93xx_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg)
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{
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struct intrq* iq;
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struct intrhand* ih;
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u_int oldirqstate;
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if (irq < 0 || irq > NIRQ)
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panic("ep93xx_intr_establish: IRQ %d out of range", irq);
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if (ipl < 0 || ipl > NIPL)
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panic("ep93xx_intr_establish: IPL %d out of range", ipl);
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_func = ih_func;
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ih->ih_arg = arg;
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ih->ih_irq = irq;
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ih->ih_ipl = ipl;
|
||||
|
||||
iq = &intrq[irq];
|
||||
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
|
||||
ep93xx_intr_calculate_masks();
|
||||
restore_interrupts(oldirqstate);
|
||||
|
||||
return (ih);
|
||||
}
|
||||
|
||||
void
|
||||
ep93xx_intr_disestablish(void *cookie)
|
||||
{
|
||||
struct intrhand* ih = cookie;
|
||||
struct intrq* iq = &intrq[ih->ih_irq];
|
||||
u_int oldirqstate;
|
||||
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
|
||||
ep93xx_intr_calculate_masks();
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
void
|
||||
ep93xx_intr_dispatch(struct clockframe *frame)
|
||||
{
|
||||
struct intrq* iq;
|
||||
struct intrhand* ih;
|
||||
u_int oldirqstate;
|
||||
int pcpl;
|
||||
u_int32_t vic1_hwpend;
|
||||
u_int32_t vic2_hwpend;
|
||||
int irq;
|
||||
u_int32_t ibit;
|
||||
|
||||
pcpl = current_spl_level;
|
||||
|
||||
vic1_hwpend = VIC1REG(EP93XX_VIC_IRQStatus);
|
||||
vic2_hwpend = VIC2REG(EP93XX_VIC_IRQStatus);
|
||||
|
||||
hardware_spl_level = pcpl;
|
||||
ep93xx_set_intrmask(vic1_imask[pcpl] | vic1_hwpend,
|
||||
vic2_imask[pcpl] | vic2_hwpend);
|
||||
|
||||
vic1_hwpend &= ~vic1_imask[pcpl];
|
||||
vic2_hwpend &= ~vic2_imask[pcpl];
|
||||
|
||||
while (vic1_hwpend) {
|
||||
irq = ffs(vic1_hwpend) - 1;
|
||||
ibit = (1U << irq);
|
||||
|
||||
iq = &intrq[irq];
|
||||
iq->iq_ev.ev_count++;
|
||||
uvmexp.intrs++;
|
||||
for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
|
||||
ih = TAILQ_NEXT(ih, ih_list)) {
|
||||
int ipl;
|
||||
|
||||
current_spl_level = ipl = ih->ih_ipl;
|
||||
oldirqstate = enable_interrupts(I32_bit);
|
||||
(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
|
||||
restore_interrupts(oldirqstate);
|
||||
vic1_hwpend &= ~ibit;
|
||||
}
|
||||
}
|
||||
while (vic2_hwpend) {
|
||||
irq = ffs(vic2_hwpend) - 1;
|
||||
ibit = (1U << irq);
|
||||
|
||||
iq = &intrq[irq + VIC_NIRQ];
|
||||
iq->iq_ev.ev_count++;
|
||||
uvmexp.intrs++;
|
||||
for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
|
||||
ih = TAILQ_NEXT(ih, ih_list)) {
|
||||
int ipl;
|
||||
|
||||
current_spl_level = ipl = ih->ih_ipl;
|
||||
oldirqstate = enable_interrupts(I32_bit);
|
||||
(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
|
||||
restore_interrupts(oldirqstate);
|
||||
vic2_hwpend &= ~ibit;
|
||||
}
|
||||
}
|
||||
|
||||
current_spl_level = pcpl;
|
||||
hardware_spl_level = pcpl;
|
||||
ep93xx_set_intrmask(vic1_imask[pcpl], vic2_imask[pcpl]);
|
||||
|
||||
/* Check for pendings soft intrs. */
|
||||
if ((ipending & INT_SWMASK) & ~vic1_imask[pcpl]) {
|
||||
oldirqstate = enable_interrupts(I32_bit);
|
||||
ep93xx_do_pending();
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
}
|
||||
50
sys/arch/arm/ep93xx/ep93xx_intr.h
Normal file
50
sys/arch/arm/ep93xx/ep93xx_intr.h
Normal file
@ -0,0 +1,50 @@
|
||||
/* $NetBSD: ep93xx_intr.h,v 1.1 2004/12/22 19:07:14 joff Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Jesse Off
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _EP93XX_INTR_H_
|
||||
#define _EP93XX_INTR_H_
|
||||
|
||||
#define ARM_IRQ_HANDLER _C_LABEL(ep93xx_intr_dispatch)
|
||||
|
||||
#ifndef _LOCORE
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
void _setsoftintr(int);
|
||||
|
||||
#endif /* ! _LOCORE */
|
||||
|
||||
#endif /* _EP93XX_INTR_H_ */
|
||||
Loading…
Reference in New Issue
Block a user