- store the maximum [id]cache size / line size for each cpu
- remove patch_kernel() since it isn't necessary and has been patching the wrong thing in general. - implement USIII versions of blast_icache(), dcache_flush_page() and cache_flush_phys(). use the newly recorded cache size/line sizes. - in winfixsave, flush the D$ with the right size index and ops. this kills one of the wrong tag->inval patches. - for blast_dcache(), use the newly recorded dcache_size/line_size. - for blast_icache(), use the newly recorded cache size/line sizes. for the USIII verison, disable the I$ while writing to ASI_ICACHE_TAG. these changes removed several hard coded cache sizes values, some very wrong kernel patching, and seem to make the current failure modes for USIII less common, but not gone.
This commit is contained in:
mrg
parent
59afab0ca6
commit
9181dd2c07
@ -1,4 +1,4 @@
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/* $NetBSD: autoconf.c,v 1.167 2010/02/15 07:56:51 mrg Exp $ */
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/* $NetBSD: autoconf.c,v 1.168 2010/02/22 00:16:31 mrg Exp $ */
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/*
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* Copyright (c) 1996
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@ -48,7 +48,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.167 2010/02/15 07:56:51 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.168 2010/02/22 00:16:31 mrg Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -183,7 +183,6 @@ int autoconf_debug = 0x0;
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#endif
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int console_node, console_instance;
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static void patch_kernel(void);
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struct genfb_colormap_callback gfb_cb;
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static void of_set_palette(void *, int, int, int, int);
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static void copyprops(struct device *busdev, int, prop_dictionary_t);
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@ -335,65 +334,6 @@ die_old_boot_loader:
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get_ncpus();
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pmap_bootstrap(KERNBASE, bi_kend->addr);
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patch_kernel();
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}
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/*
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* Now that we've stopped using the prom mappings, we need to handle any
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* text fixups.
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*
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* For the USIII and newer cpus, convert ASI_DCACHE_TAG into
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* ASI_DCACHE_INVALIDATE.
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*
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* For the older CPUs, we need to convert a branch to a nop in
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* cache_flush_phys().
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*/
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static void
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patch_kernel(void)
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{
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paddr_t pa;
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vaddr_t *pva;
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if (CPU_IS_USIII_UP()) {
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extern vaddr_t dlflush_start;
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uint32_t insn, oinsn;
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for (pva = &dlflush_start; *pva; pva++) {
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oinsn = insn = *(uint32_t *)(*pva);
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insn &= ~(ASI_DCACHE_TAG << 5);
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insn |= (ASI_DCACHE_INVALIDATE << 5);
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if (pmap_extract(pmap_kernel(), *pva, &pa)) {
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sta(pa, ASI_PHYS_CACHED, insn);
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flush((void *)(*pva));
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#ifdef PATCH_KERNEL_DEBUG
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printf("patched %p for USIII ASI_DCACHE_INVALIDATE"
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": old insn %08x ew insn %08x\n",
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(void *)(intptr_t)*pva, oinsn, insn);
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} else {
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printf("could not pmap_extract() to patch %p\n",
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(void *)(intptr_t)*pva);
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#endif
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}
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}
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} else {
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extern vaddr_t nop_on_us_1_start;
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for (pva = &nop_on_us_1_start; *pva; pva++) {
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if (pmap_extract(pmap_kernel(), *pva, &pa)) {
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sta(pa, ASI_PHYS_CACHED, 0x01000000);
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flush((void *)(*pva));
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#ifdef PATCH_KERNEL_DEBUG
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printf("patched %p for USI/II cache_flush_phys\n",
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(void *)(intptr_t)*pva);
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} else {
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printf("could not pmap_extract() to patch %p\n",
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(void *)(intptr_t)*pva);
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#endif
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}
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}
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}
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}
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.11 2010/02/01 03:43:27 mrg Exp $ */
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/* $NetBSD: cache.h,v 1.12 2010/02/22 00:16:31 mrg Exp $ */
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/*
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* Copyright (c) 1996
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@ -73,12 +73,46 @@
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*/
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/* The following are for I$ and D$ flushes and are in locore.s */
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void dcache_flush_page(paddr_t); /* flush page from D$ */
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void dcache_flush_page_us(paddr_t); /* flush page from D$ */
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void dcache_flush_page_usiii(paddr_t); /* flush page from D$ */
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void blast_dcache(void); /* Clear entire D$ */
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void blast_icache(void); /* Clear entire I$ */
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void blast_icache_us(void); /* Clear entire I$ */
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void blast_icache_usiii(void); /* Clear entire I$ */
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/* The following flush a range from the D$ and I$ but not E$. */
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void cache_flush_phys(paddr_t, psize_t, int);
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void cache_flush_phys_us(paddr_t, psize_t, int);
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void cache_flush_phys_usiii(paddr_t, psize_t, int);
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/* Smallest E$ line size. */
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static __inline__ void
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dcache_flush_page(paddr_t pa)
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{
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if (CPU_IS_USIII_UP())
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dcache_flush_page_usiii(pa);
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else
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dcache_flush_page_us(pa);
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}
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static __inline__ void
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cache_flush_phys(paddr_t pa, psize_t size, int ecache)
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{
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if (CPU_IS_USIII_UP())
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cache_flush_phys_usiii(pa, size, ecache);
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else
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cache_flush_phys_us(pa, size, ecache);
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}
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static __inline__ void
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blast_icache(void)
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{
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if (CPU_IS_USIII_UP())
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blast_icache_usiii();
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else
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blast_icache_us();
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}
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/* Various cache size/line sizes */
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extern int ecache_min_line_size;
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extern int dcache_line_size;
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extern int dcache_size;
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extern int icache_line_size;
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extern int icache_size;
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.88 2009/12/02 07:55:01 mrg Exp $ */
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/* $NetBSD: cpu.c,v 1.89 2010/02/22 00:16:31 mrg Exp $ */
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/*
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* Copyright (c) 1996
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@ -52,7 +52,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.88 2009/12/02 07:55:01 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.89 2010/02/22 00:16:31 mrg Exp $");
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#include "opt_multiprocessor.h"
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@ -92,6 +92,12 @@ char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
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char cpu_model[100]; /* machine model (primary CPU) */
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extern char machine_model[];
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/* These are used in locore.s, and are maximums */
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int dcache_line_size;
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int dcache_size;
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int icache_line_size;
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int icache_size;
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#ifdef MULTIPROCESSOR
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static const char *ipi_evcnt_names[IPI_EVCNT_NUM] = IPI_EVCNT_NAMES;
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#endif
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@ -238,7 +244,7 @@ cpu_attach(struct device *parent, struct device *dev, void *aux)
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int bigcache, cachesize;
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char buf[100];
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int totalsize = 0;
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int linesize;
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int linesize, dcachesize, icachesize;
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/* tell them what we have */
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node = ma->ma_node;
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@ -295,14 +301,18 @@ cpu_attach(struct device *parent, struct device *dev, void *aux)
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bigcache = 0;
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linesize = l =
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prom_getpropint(node, "icache-line-size", 0);
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icachesize = prom_getpropint(node, "icache-size", 0);
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if (icachesize > icache_size)
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icache_size = icachesize;
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linesize = l = prom_getpropint(node, "icache-line-size", 0);
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if (linesize > icache_line_size)
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icache_line_size = linesize;
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for (i = 0; (1 << i) < l && l; i++)
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/* void */;
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if ((1 << i) != l && l)
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panic("bad icache line size %d", l);
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totalsize =
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prom_getpropint(node, "icache-size", 0) *
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totalsize = icachesize *
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prom_getpropint(node, "icache-associativity", 1);
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if (totalsize == 0)
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totalsize = l *
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@ -321,14 +331,18 @@ cpu_attach(struct device *parent, struct device *dev, void *aux)
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sep = ", ";
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}
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linesize = l =
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prom_getpropint(node, "dcache-line-size",0);
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dcachesize = prom_getpropint(node, "dcache-size", 0);
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if (dcachesize > dcache_size)
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dcache_size = dcachesize;
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linesize = l = prom_getpropint(node, "dcache-line-size", 0);
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if (linesize > dcache_line_size)
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dcache_line_size = linesize;
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for (i = 0; (1 << i) < l && l; i++)
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/* void */;
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if ((1 << i) != l && l)
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panic("bad dcache line size %d", l);
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totalsize =
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prom_getpropint(node, "dcache-size", 0) *
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totalsize = dcachesize *
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prom_getpropint(node, "dcache-associativity", 1);
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if (totalsize == 0)
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totalsize = l *
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.317 2010/02/15 12:46:24 mrg Exp $ */
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/* $NetBSD: locore.s,v 1.318 2010/02/22 00:16:31 mrg Exp $ */
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/*
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* Copyright (c) 1996-2002 Eduardo Horvath
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@ -61,7 +61,6 @@
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#undef TRAPS_USE_IG /* Use Interrupt Globals for all traps */
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#define HWREF /* Track ref/mod bits in trap handlers */
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#undef DCACHE_BUG /* Flush D$ around ASI_PHYS accesses */
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#undef SPITFIRE /* Only used in DLFLUSH* now, see DCACHE_BUG */
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#undef NO_TSB /* Don't use TSB */
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#define USE_BLOCK_STORE_LOAD /* enable block load/store ops */
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#define BB_ERRATA_1 /* writes to TICK_CMPR may fail */
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@ -202,20 +201,14 @@
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* It uses a register with the address to clear and a temporary
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* which is destroyed.
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*/
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#ifdef SPITFIRE
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#define ASI_DCACHE_TAG_OR_INV ASI_DCACHE_TAG
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#else
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#define ASI_DCACHE_TAG_OR_INV ASI_DCACHE_INVALIDATE
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#endif
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#ifdef DCACHE_BUG
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#define DLFLUSH(a,t) \
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andn a, 0x1f, t; \
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stxa %g0, [ t ] ASI_DCACHE_TAG_OR_INV; \
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stxa %g0, [ t ] ASI_DCACHE_TAG; \
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membar #Sync
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/* The following can be used if the pointer is 16-byte aligned */
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#define DLFLUSH2(t) \
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stxa %g0, [ t ] ASI_DCACHE_TAG_OR_INV; \
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stxa %g0, [ t ] ASI_DCACHE_TAG; \
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membar #Sync
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#else
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#define DLFLUSH(a,t)
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@ -2285,9 +2278,12 @@ winfixsave:
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/* Did we save a user or kernel window ? */
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! srax %g3, 48, %g5 ! User or kernel store? (TAG TARGET)
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sllx %g3, (64-13), %g5 ! User or kernel store? (TAG ACCESS)
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sethi %hi((2*NBPG)-8), %g7
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sethi %hi(dcache_size), %g7
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ld [%g7 + %lo(dcache_size)], %g7
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sethi %hi(dcache_line_size), %g6
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ld [%g6 + %lo(dcache_line_size)], %g6
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brnz,pt %g5, 1f ! User fault -- save windows to pcb
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or %g7, %lo((2*NBPG)-8), %g7
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sub %g7, %g6, %g7
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and %g4, CWP, %g4 ! %g4 = %cwp of trap
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wrpr %g4, 0, %cwp ! Kernel fault -- restore %cwp and force and trap to debugger
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@ -2316,10 +2312,9 @@ winfixsave:
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1:
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#if 1
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/* Now we need to blast away the D$ to make sure we're in sync */
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dlflush1:
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stxa %g0, [%g7] ASI_DCACHE_TAG
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brnz,pt %g7, 1b
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dec 8, %g7
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sub %g7, %g6, %g7
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#endif
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#ifdef NOTDEF_DEBUG
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@ -5296,14 +5291,19 @@ ENTRY(blast_dcache)
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#endif
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rdpr %pstate, %o3
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set (2 * NBPG) - 32, %o1
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sethi %hi(dcache_size), %o1
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ld [%o1 + %lo(dcache_size)], %o1
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sethi %hi(dcache_line_size), %o5
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ld [%o5 + %lo(dcache_line_size)], %o5
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sub %o1, %o5, %o1
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andn %o3, PSTATE_IE, %o4 ! Turn off PSTATE_IE bit
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wrpr %o4, 0, %pstate
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1:
|
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dlflush2:
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stxa %g0, [%o1] ASI_DCACHE_TAG
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membar #Sync
|
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brnz,pt %o1, 1b
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dec 32, %o1
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sub %o1, %o5, %o1
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sethi %hi(KERNBASE), %o2
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flush %o2
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membar #Sync
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@ -5317,39 +5317,69 @@ dlflush2:
|
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#endif
|
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|
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/*
|
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* blast_icache()
|
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* blast_icache_us()
|
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* blast_icache_usiii()
|
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*
|
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* Clear out all of I$ regardless of contents
|
||||
* Does not modify %o0
|
||||
*
|
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* We turn off interrupts for the duration to prevent RED exceptions.
|
||||
* For the Cheetah version, we also have to to turn off the I$ during this as
|
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* ASI_ICACHE_TAG accesses interfere with coherency.
|
||||
*/
|
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.align 8
|
||||
ENTRY(blast_icache)
|
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/*
|
||||
* We turn off interrupts for the duration to prevent RED exceptions.
|
||||
*/
|
||||
ENTRY(blast_icache_us)
|
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rdpr %pstate, %o3
|
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set (2 * NBPG) - 32, %o1
|
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sethi %hi(icache_size), %o1
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ld [%o1 + %lo(icache_size)], %o1
|
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sethi %hi(icache_line_size), %o2
|
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ld [%o2 + %lo(icache_line_size)], %o2
|
||||
sub %o1, %o2, %o1
|
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andn %o3, PSTATE_IE, %o4 ! Turn off PSTATE_IE bit
|
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wrpr %o4, 0, %pstate
|
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1:
|
||||
stxa %g0, [%o1] ASI_ICACHE_TAG
|
||||
brnz,pt %o1, 1b
|
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dec 32, %o1
|
||||
sethi %hi(KERNBASE), %o2
|
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flush %o2
|
||||
sub %o1, %o2, %o1
|
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sethi %hi(KERNBASE), %o5
|
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flush %o5
|
||||
membar #Sync
|
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retl
|
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wrpr %o3, %pstate
|
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|
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.align 8
|
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ENTRY(blast_icache_usiii)
|
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rdpr %pstate, %o3
|
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sethi %hi(icache_size), %o1
|
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ld [%o1 + %lo(icache_size)], %o1
|
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sethi %hi(icache_line_size), %o2
|
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ld [%o2 + %lo(icache_line_size)], %o2
|
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sub %o1, %o2, %o1
|
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andn %o3, PSTATE_IE, %o4 ! Turn off PSTATE_IE bit
|
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wrpr %o4, 0, %pstate
|
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ldxa [%g0] ASI_MCCR, %o5
|
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andn %o5, MCCR_ICACHE_EN, %o4 ! Turn off the I$
|
||||
stxa %o4, [%g0] ASI_MCCR
|
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flush %g0
|
||||
1:
|
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stxa %g0, [%o1] ASI_ICACHE_TAG
|
||||
membar #Sync
|
||||
brnz,pt %o1, 1b
|
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sub %o1, %o2, %o1
|
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stxa %o5, [%g0] ASI_MCCR ! Restore the I$
|
||||
flush %g0
|
||||
retl
|
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wrpr %o3, %pstate
|
||||
|
||||
/*
|
||||
* dcache_flush_page(paddr_t pa)
|
||||
* dcache_flush_page_us(paddr_t pa)
|
||||
* dcache_flush_page_usiii(paddr_t pa)
|
||||
*
|
||||
* Clear one page from D$.
|
||||
*
|
||||
*/
|
||||
.align 8
|
||||
ENTRY(dcache_flush_page)
|
||||
ENTRY(dcache_flush_page_us)
|
||||
#ifndef _LP64
|
||||
COMBINE(%o0, %o1, %o0)
|
||||
#endif
|
||||
@ -5374,7 +5404,6 @@ ENTRY(dcache_flush_page)
|
||||
bne,pt %xcc, 1b
|
||||
membar #LoadStore
|
||||
|
||||
dlflush3:
|
||||
stxa %g0, [%o0] ASI_DCACHE_TAG
|
||||
ba,pt %icc, 1b
|
||||
membar #StoreLoad
|
||||
@ -5385,15 +5414,38 @@ dlflush3:
|
||||
retl
|
||||
membar #Sync
|
||||
|
||||
.align 8
|
||||
ENTRY(dcache_flush_page_usiii)
|
||||
#ifndef _LP64
|
||||
COMBINE(%o0, %o1, %o0)
|
||||
#endif
|
||||
set NBPG, %o1
|
||||
sethi %hi(dcache_line_size), %o2
|
||||
add %o0, %o1, %o1 ! end address
|
||||
ld [%o2 + %lo(dcache_line_size)], %o2
|
||||
|
||||
1:
|
||||
stxa %g0, [%o0] ASI_DCACHE_INVALIDATE
|
||||
add %o0, %o2, %o0
|
||||
cmp %o0, %o1
|
||||
bl,pt %xcc, 1b
|
||||
nop
|
||||
|
||||
sethi %hi(KERNBASE), %o5
|
||||
flush %o5
|
||||
retl
|
||||
membar #Sync
|
||||
|
||||
/*
|
||||
* cache_flush_phys(paddr_t, psize_t, int);
|
||||
* cache_flush_phys_us(paddr_t, psize_t, int);
|
||||
* cache_flush_phys_usiii(paddr_t, psize_t, int);
|
||||
*
|
||||
* Clear a set of paddrs from the D$, I$ and if param3 is
|
||||
* non-zero, E$. (E$ is not supported yet).
|
||||
*/
|
||||
|
||||
.align 8
|
||||
ENTRY(cache_flush_phys)
|
||||
ENTRY(cache_flush_phys_us)
|
||||
#ifndef _LP64
|
||||
COMBINE(%o0, %o1, %o0)
|
||||
COMBINE(%o2, %o3, %o1)
|
||||
@ -5433,13 +5485,9 @@ ENTRY(cache_flush_phys)
|
||||
nop
|
||||
|
||||
membar #LoadStore
|
||||
dlflush4:
|
||||
stxa %g0, [%o4] ASI_DCACHE_TAG ! Just right
|
||||
membar #Sync
|
||||
2:
|
||||
nop_on_us_1:
|
||||
b 3f
|
||||
nop ! XXXMRG put something useful here?
|
||||
ldda [%o4] ASI_ICACHE_TAG, %g0 ! Tag goes in %g1
|
||||
sllx %g1, 40-35, %g1 ! Shift I$ tag into place
|
||||
and %g1, %o2, %g1 ! Mask out trash
|
||||
@ -5457,10 +5505,37 @@ nop_on_us_1:
|
||||
|
||||
sethi %hi(KERNBASE), %o5
|
||||
flush %o5
|
||||
membar #Sync
|
||||
retl
|
||||
membar #Sync
|
||||
|
||||
.align 8
|
||||
ENTRY(cache_flush_phys_usiii)
|
||||
#ifndef _LP64
|
||||
COMBINE(%o0, %o1, %o0)
|
||||
COMBINE(%o2, %o3, %o1)
|
||||
mov %o4, %o2
|
||||
#endif
|
||||
#ifdef DEBUG
|
||||
tst %o2 ! Want to clear E$?
|
||||
tnz 1 ! Error!
|
||||
#endif
|
||||
add %o0, %o1, %o1 ! End PA
|
||||
sethi %hi(dcache_line_size), %o3
|
||||
ld [%o3 + %lo(dcache_line_size)], %o3
|
||||
sethi %hi(KERNBASE), %o5
|
||||
1:
|
||||
stxa %g0, [%o0] ASI_DCACHE_INVALIDATE
|
||||
add %o0, %o3, %o0
|
||||
cmp %o0, %o1
|
||||
bl,pt %xcc, 1b
|
||||
nop
|
||||
|
||||
/* don't need to flush the I$ on cheetah */
|
||||
|
||||
flush %o5
|
||||
retl
|
||||
membar #Sync
|
||||
|
||||
#ifdef COMPAT_16
|
||||
#ifdef _LP64
|
||||
/*
|
||||
@ -9694,16 +9769,3 @@ _C_LABEL(ssym):
|
||||
.comm _C_LABEL(trapdebug), 4
|
||||
.comm _C_LABEL(pmapdebug), 4
|
||||
#endif
|
||||
|
||||
.globl _C_LABEL(dlflush_start)
|
||||
_C_LABEL(dlflush_start):
|
||||
POINTER dlflush1
|
||||
POINTER dlflush2
|
||||
POINTER dlflush3
|
||||
POINTER dlflush4
|
||||
POINTER 0
|
||||
|
||||
.globl _C_LABEL(nop_on_us_1_start)
|
||||
_C_LABEL(nop_on_us_1_start):
|
||||
POINTER nop_on_us_1
|
||||
POINTER 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user