Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

space/tab cosmetics

Browse Source
This commit is contained in:
tsutsui 2001-02-11 17:49:08 +00:00
parent 18d584f8ef
commit 90fc74c95b
3 changed files with 23 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
sys/arch/pmax/pmax/dec_3min.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_3min.c,v 1.43 2000/10/05 02:36:45 cgd Exp $ */
/* $NetBSD: dec_3min.c,v 1.44 2001/02/11 17:49:08 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.43 2000/10/05 02:36:45 cgd Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.44 2001/02/11 17:49:08 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -142,7 +142,7 @@ dec_3min_init()
* TURBOchannel option slots, just splhigh().
*/
splvec.splbio = MIPS_SPL_0_1_2_3;
splvec.splnet = MIPS_SPL_0_1_2_3;
splvec.splnet = MIPS_SPL_0_1_2_3;
splvec.spltty = MIPS_SPL_0_1_2_3;
splvec.splimp = MIPS_SPL_0_1_2_3;
splvec.splclock = MIPS_SPL_0_1_2_3;
@ -150,17 +150,17 @@ dec_3min_init()
/* enable posting of MIPS_INT_MASK_3 to CAUSE register */
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK;
/* calibrate cpu_mhz value */
/* calibrate cpu_mhz value */
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3);
*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
#if 0
#if 0
*(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
*(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
#endif
#endif
/* sanitize interrupt mask */
kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT);
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
@ -311,12 +311,12 @@ dec_3min_intr_establish(dev, cookie, level, handler, arg)
}
#define CHECKINTR(slot, bits) \
#define CHECKINTR(slot, bits) \
do { \
if (can_serve & (bits)) { \
intrcnt[slot] += 1; \
(*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \
} \
if (can_serve & (bits)) { \
intrcnt[slot] += 1; \
(*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \
} \
} while (0)
static void

8
sys/arch/pmax/pmax/dec_5100.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_5100.c,v 1.26 2000/06/06 00:08:25 nisimura Exp $ */
/* $NetBSD: dec_5100.c,v 1.27 2001/02/11 17:49:08 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_5100.c,v 1.26 2000/06/06 00:08:25 nisimura Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_5100.c,v 1.27 2001/02/11 17:49:08 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -76,7 +76,7 @@ dec_5100_init()
splvec.splbio = MIPS_SPL1;
splvec.splnet = MIPS_SPL1;
splvec.spltty = MIPS_SPL_0_1;
splvec.spltty = MIPS_SPL_0_1;
splvec.splimp = MIPS_SPL_0_1_2;
splvec.splclock = MIPS_SPL_0_1_2;
splvec.splstatclock = MIPS_SPL_0_1_2;
@ -215,7 +215,7 @@ dec_5100_memintr()
kn230_wbflush();
#ifdef DIAGNOSTIC
printf("\nMemory interrupt\n");
printf("\nMemory interrupt\n");
#endif
/* ignore errors during probes */

15
sys/arch/pmax/pmax/dec_maxine.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_maxine.c,v 1.34 2000/06/06 00:08:26 nisimura Exp $ */
/* $NetBSD: dec_maxine.c,v 1.35 2001/02/11 17:49:08 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.34 2000/06/06 00:08:26 nisimura Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.35 2001/02/11 17:49:08 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -272,7 +272,6 @@ dec_maxine_intr_establish(dev, cookie, level, handler, arg)
kn02ca_wbflush();
}
#define CHECKINTR(vvv, bits) \
do { \
if (can_serve & (bits)) { \
@ -314,13 +313,13 @@ dec_maxine_intr(status, cause, pc, ipending)
if (ipending & MIPS_INT_MASK_3) {
int ifound;
u_int32_t imsk, intr, can_serve, xxxintr;
do {
ifound = 0;
intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR);
imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
can_serve = intr & imsk;
CHECKINTR(SYS_DEV_DTOP, XINE_INTR_DTOP);
CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0);
CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE);
@ -328,8 +327,8 @@ dec_maxine_intr(status, cause, pc, ipending)
/* CHECKINTR(SYS_DEV_OPT2, XINE_INTR_VINT); */
CHECKINTR(SYS_DEV_ISDN, (IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD));
/* CHECKINTR(SYS_DEV_FDC, IOASIC_INTR_FDC); */
CHECKINTR(SYS_DEV_OPT1, XINE_INTR_TC_1);
CHECKINTR(SYS_DEV_OPT0, XINE_INTR_TC_0);
CHECKINTR(SYS_DEV_OPT1, XINE_INTR_TC_1);
CHECKINTR(SYS_DEV_OPT0, XINE_INTR_TC_0);
#define ERRORS (IOASIC_INTR_ISDN_OVRUN|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E|IOASIC_INTR_LANCE_READ_E)
#define PTRLOAD (IOASIC_INTR_ISDN_TXLOAD|IOASIC_INTR_ISDN_RXLOAD|IOASIC_INTR_SCSI_PTR_LOAD)
@ -385,7 +384,7 @@ static unsigned
kn02ca_clkread()
{
u_int32_t cycles;
cycles = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR);
return cycles - latched_cycle_cnt;
}