add NAND module clock
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6a8980245d
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@ -1,4 +1,4 @@
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/* $NetBSD: sun4i_a10_ccu.c,v 1.4 2017/10/09 14:01:59 jmcneill Exp $ */
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/* $NetBSD: sun4i_a10_ccu.c,v 1.5 2017/11/13 15:01:16 jmcneill Exp $ */
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/*-
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* Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
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@ -28,7 +28,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.4 2017/10/09 14:01:59 jmcneill Exp $");
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__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.5 2017/11/13 15:01:16 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -51,6 +51,7 @@ __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.4 2017/10/09 14:01:59 jmcneill E
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#define AHB_GATING_REG1 0x064
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#define APB0_GATING_REG 0x068
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#define APB1_GATING_REG 0x06c
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#define NAND_SCLK_CFG_REG 0x080
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#define SD0_SCLK_CFG_REG 0x088
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#define SD1_SCLK_CFG_REG 0x08c
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#define SD2_SCLK_CFG_REG 0x090
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@ -200,6 +201,14 @@ static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = {
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0, /* enable */
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SUNXI_CCU_NM_POWER_OF_TWO),
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SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents,
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NAND_SCLK_CFG_REG, /* reg */
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__BITS(17,16), /* n */
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__BITS(3,0), /* m */
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__BITS(25,24), /* sel */
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__BIT(31), /* enable */
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SUNXI_CCU_NM_POWER_OF_TWO),
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SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents,
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SD0_SCLK_CFG_REG, /* reg */
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__BITS(17,16), /* n */
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