Reclaim PVF_KNC in VIPT to be PVF_MULTCLR (page has multiple colors).
Track when a page is mapping in multiple colors and deal with the ramifications. When a page's MOD attribute is cleared, clean it from the cache. Fix a logic inversion. With these changes, the TI SDP2420 H4 board can successfully natively build a TISDP2420 kernel.
This commit is contained in:
matt
parent
a7cf4e5ecd
commit
8f704298aa
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.193 2008/12/10 11:10:18 pooka Exp $ */
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/* $NetBSD: pmap.c,v 1.194 2008/12/30 05:51:19 matt Exp $ */
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/*
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* Copyright 2003 Wasabi Systems, Inc.
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@ -212,7 +212,7 @@
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#include <machine/param.h>
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#include <arm/arm32/katelib.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.193 2008/12/10 11:10:18 pooka Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.194 2008/12/30 05:51:19 matt Exp $");
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#ifdef PMAP_DEBUG
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@ -310,6 +310,16 @@ static paddr_t pmap_kernel_l2ptp_phys;
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EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name)
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#ifdef PMAP_CACHE_VIPT
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static struct evcnt pmap_ev_vac_clean_one =
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PMAP_EVCNT_INITIALIZER("clean page (1 color)");
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static struct evcnt pmap_ev_vac_flush_one =
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PMAP_EVCNT_INITIALIZER("flush page (1 color)");
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static struct evcnt pmap_ev_vac_flush_lots =
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PMAP_EVCNT_INITIALIZER("flush page (2+ colors)");
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EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one);
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EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one);
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EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots);
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static struct evcnt pmap_ev_vac_color_new =
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PMAP_EVCNT_INITIALIZER("new page color");
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static struct evcnt pmap_ev_vac_color_reuse =
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@ -656,7 +666,12 @@ static int pmap_clean_page(struct pv_entry *, bool);
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#endif
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#ifdef PMAP_CACHE_VIPT
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static void pmap_syncicache_page(struct vm_page *);
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static void pmap_flush_page(struct vm_page *, bool);
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enum pmap_flush_op {
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PMAP_FLUSH_PRIMARY,
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PMAP_FLUSH_SECONDARY,
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PMAP_CLEAN_PRIMARY
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};
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static void pmap_flush_page(struct vm_page *, enum pmap_flush_op);
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#endif
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static void pmap_page_remove(struct vm_page *);
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@ -1005,7 +1020,7 @@ pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, int skip_wired)
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* clear the KMOD attribute from the page.
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*/
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if (SLIST_FIRST(&pg->mdpage.pvh_list) == NULL
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|| (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) == PVF_KWRITE)
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|| (SLIST_FIRST(&pg->mdpage.pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE)
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pg->mdpage.pvh_attrs &= ~PVF_KMOD;
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/*
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@ -1798,36 +1813,6 @@ pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va)
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#endif
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#ifdef PMAP_CACHE_VIPT
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/*
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* For virtually indexed / physically tagged caches, what we have to worry
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* about is illegal cache aliases. To prevent this, we must ensure that
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* virtual addresses that map the physical page use the same bits for those
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* bits masked by "arm_cache_prefer_mask" (bits 12+). If there is a conflict,
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* all mappings of the page must be non-cached.
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*/
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#if 0
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static inline vaddr_t
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pmap_check_sets(paddr_t pa)
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{
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extern int arm_dcache_l2_nsets;
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int set, way;
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vaddr_t mask = 0;
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int v;
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pa |= 1;
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for (set = 0; set < (1 << arm_dcache_l2_nsets); set++) {
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for (way = 0; way < 4; way++) {
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v = (way << 30) | (set << 5);
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asm("mcr p15, 3, %0, c15, c2, 0" :: "r"(v));
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asm("mrc p15, 3, %0, c15, c0, 0" : "=r"(v));
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if ((v & (1 | ~(PAGE_SIZE-1))) == pa) {
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mask |= 1 << (set >> 7);
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}
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}
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}
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return mask;
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}
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#endif
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static void
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pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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{
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@ -1847,13 +1832,6 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: pg=%p, pmap=%p va=%08lx\n",
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pg, pm, va));
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#define popc4(x) \
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(((0x94 >> ((x & 3) << 1)) & 3) + ((0x94 >> ((x & 12) >> 1)) & 3))
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#if 0
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tst_mask = pmap_check_sets(pg->phys_addr);
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KASSERT(popc4(tst_mask) < 2);
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#endif
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KASSERT(!va || pm);
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KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC)));
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@ -1891,8 +1869,28 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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if (!bad_alias)
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pg->mdpage.pvh_attrs |= PVF_DIRTY;
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} else {
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/*
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* We have only read-only mappings. Let's see if there
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* are multiple colors in use or if we mapped a KMPAGE.
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* If the latter, we have a bad alias. If the former,
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* we need to remember that.
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*/
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for (; pv; pv = SLIST_NEXT(pv, pv_link)) {
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if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) {
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if (pg->mdpage.pvh_attrs & PVF_KMPAGE)
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bad_alias = true;
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break;
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}
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}
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pg->mdpage.pvh_attrs &= ~PVF_WRITE;
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/*
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* No KMPAGE and we exited early, so we must have
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* multiple color mappings.
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*/
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if (!bad_alias && pv != NULL)
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pg->mdpage.pvh_attrs |= PVF_MULTCLR;
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}
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/* If no conflicting colors, set everything back to cached */
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if (!bad_alias) {
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#ifdef DEBUG
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@ -1901,7 +1899,6 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link)
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KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0);
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}
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#endif
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pg->mdpage.pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC;
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pg->mdpage.pvh_attrs |= tst_mask | PVF_COLORED;
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@ -1921,8 +1918,25 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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KASSERT(pmap_is_page_colored_p(pg));
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KASSERT(!(pg->mdpage.pvh_attrs & PVF_WRITE)
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|| (pg->mdpage.pvh_attrs & PVF_DIRTY));
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if (rw_mappings == 0)
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if (rw_mappings == 0) {
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pg->mdpage.pvh_attrs &= ~PVF_WRITE;
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if (ro_mappings == 1
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&& (pg->mdpage.pvh_attrs & PVF_MULTCLR)) {
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/*
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* If this is the last readonly mapping
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* but it doesn't match the current color
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* for the page, change the current color
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* to match this last readonly mapping.
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*/
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pv = SLIST_FIRST(&pg->mdpage.pvh_list);
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tst_mask = (pg->mdpage.pvh_attrs ^ pv->pv_va)
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& arm_cache_prefer_mask;
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if (tst_mask) {
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pg->mdpage.pvh_attrs ^= tst_mask;
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PMAPCOUNT(vac_color_change);
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}
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}
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}
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KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC)));
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KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE));
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return;
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@ -1941,20 +1955,22 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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bad_alias = false;
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if (rw_mappings > 0) {
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/*
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* We now have writeable mappings and more than one
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* readonly mapping, verify the colors don't clash
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* and mark the page as writeable.
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* We now have writeable mappings and if we have
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* readonly mappings in more than once color, we have
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* an aliasing problem. Regardless mark the page as
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* writeable.
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*/
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if (ro_mappings > 1
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&& (pg->mdpage.pvh_attrs & PVF_WRITE) == 0
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&& arm_cache_prefer_mask) {
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tst_mask = pg->mdpage.pvh_attrs & arm_cache_prefer_mask;
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SLIST_FOREACH(pv, &pg->mdpage.pvh_list, pv_link) {
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/* if there's a bad alias, stop checking. */
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if (((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0) {
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bad_alias = true;
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break;
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}
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if (pg->mdpage.pvh_attrs & PVF_MULTCLR) {
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if (ro_mappings < 2) {
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/*
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* If we only have less than two
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* read-only mappings, just flush the
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* non-primary colors from the cache.
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*/
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pmap_flush_page(pg,
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PMAP_FLUSH_SECONDARY);
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} else {
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bad_alias = true;
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}
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}
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pg->mdpage.pvh_attrs |= PVF_WRITE;
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@ -1984,7 +2000,7 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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/* color conflict. evict from cache. */
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pmap_flush_page(pg, true);
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pmap_flush_page(pg, PMAP_FLUSH_PRIMARY);
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pg->mdpage.pvh_attrs &= ~PVF_COLORED;
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pg->mdpage.pvh_attrs |= PVF_NC;
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KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC)));
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@ -1997,7 +2013,7 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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* If the page has dirty cache lines, clean it.
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*/
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if (pg->mdpage.pvh_attrs & PVF_DIRTY)
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pmap_flush_page(pg, false);
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pmap_flush_page(pg, PMAP_CLEAN_PRIMARY);
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/*
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* If this is the first remapping (we know that there are no
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@ -2013,6 +2029,7 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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} else {
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PMAPCOUNT(vac_color_blind);
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}
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pg->mdpage.pvh_attrs |= PVF_MULTCLR;
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KASSERT((pg->mdpage.pvh_attrs & PVF_DMOD) == 0 || (pg->mdpage.pvh_attrs & (PVF_DIRTY|PVF_NC)));
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KASSERT((rw_mappings == 0) == !(pg->mdpage.pvh_attrs & PVF_WRITE));
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return;
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@ -2021,7 +2038,7 @@ pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va)
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pg->mdpage.pvh_attrs |= PVF_WRITE;
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/* color conflict. evict from cache. */
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pmap_flush_page(pg, true);
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pmap_flush_page(pg, PMAP_FLUSH_PRIMARY);
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/* the list can't be empty because this was a enter/modify */
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pv = SLIST_FIRST(&pg->mdpage.pvh_list);
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@ -2438,60 +2455,93 @@ pmap_syncicache_page(struct vm_page *pg)
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}
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void
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pmap_flush_page(struct vm_page *pg, bool flush)
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pmap_flush_page(struct vm_page *pg, enum pmap_flush_op flush)
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{
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const vsize_t va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask;
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const size_t pte_offset = va_offset >> PGSHIFT;
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pt_entry_t * const ptep = &cdst_pte[pte_offset];
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const pt_entry_t oldpte = *ptep;
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#if 0
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vaddr_t mask;
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#endif
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vsize_t va_offset, end_va;
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void (*cf)(vaddr_t, vsize_t);
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KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC));
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#if 0
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mask = pmap_check_sets(pg->phys_addr);
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KASSERT(popc4(mask) < 2);
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#endif
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if (arm_cache_prefer_mask == 0)
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return;
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NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n",
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pg, pg->mdpage.pvh_attrs));
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pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset);
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/*
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* Set up a PTE with the right coloring to flush existing cache entries.
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*/
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*ptep = L2_S_PROTO
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| VM_PAGE_TO_PHYS(pg)
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| L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE)
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| pte_l2_s_cache_mode;
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PTE_SYNC(ptep);
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/*
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* Flush it.
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*/
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if (flush) {
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cpu_idcache_wbinv_range(cdstp + va_offset, PAGE_SIZE);
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switch (flush) {
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case PMAP_FLUSH_PRIMARY:
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if (pg->mdpage.pvh_attrs & PVF_MULTCLR) {
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va_offset = 0;
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end_va = arm_cache_prefer_mask;
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pg->mdpage.pvh_attrs &= ~PVF_MULTCLR;
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PMAPCOUNT(vac_flush_lots);
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} else {
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va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask;
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end_va = va_offset;
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PMAPCOUNT(vac_flush_one);
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}
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/*
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* Mark that the page is no longer dirty.
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*/
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pg->mdpage.pvh_attrs &= ~PVF_DIRTY;
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} else {
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cpu_dcache_wb_range(cdstp + va_offset, PAGE_SIZE);
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cf = cpufuncs.cf_idcache_wbinv_range;
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break;
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case PMAP_FLUSH_SECONDARY:
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va_offset = 0;
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end_va = arm_cache_prefer_mask;
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cf = cpufuncs.cf_idcache_wbinv_range;
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pg->mdpage.pvh_attrs &= ~PVF_MULTCLR;
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PMAPCOUNT(vac_flush_lots);
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break;
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case PMAP_CLEAN_PRIMARY:
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va_offset = pg->mdpage.pvh_attrs & arm_cache_prefer_mask;
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end_va = va_offset;
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cf = cpufuncs.cf_dcache_wb_range;
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/*
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* Mark that the page is no longer dirty.
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*/
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if ((pg->mdpage.pvh_attrs & PVF_DMOD) == 0)
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pg->mdpage.pvh_attrs &= ~PVF_DIRTY;
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PMAPCOUNT(vac_clean_one);
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break;
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default:
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return;
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}
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/*
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* Restore the page table entry since we might have interrupted
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* pmap_zero_page or pmap_copy_page which was already using this pte.
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*/
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*ptep = oldpte;
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PTE_SYNC(ptep);
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pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset);
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#if 0
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mask = pmap_check_sets(pg->phys_addr);
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KASSERT(mask == 0);
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#endif
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KASSERT(!(pg->mdpage.pvh_attrs & PVF_NC));
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NPDEBUG(PDB_VAC, printf("pmap_flush_page: pg=%p (attrs=%#x)\n",
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pg, pg->mdpage.pvh_attrs));
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for (; va_offset <= end_va; va_offset += PAGE_SIZE) {
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const size_t pte_offset = va_offset >> PGSHIFT;
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pt_entry_t * const ptep = &cdst_pte[pte_offset];
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const pt_entry_t oldpte = *ptep;
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if (flush == PMAP_FLUSH_SECONDARY
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&& va_offset == (pg->mdpage.pvh_attrs & arm_cache_prefer_mask))
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continue;
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pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset);
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/*
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* Set up a PTE with the right coloring to flush
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* existing cache entries.
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*/
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*ptep = L2_S_PROTO
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| VM_PAGE_TO_PHYS(pg)
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| L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE)
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| pte_l2_s_cache_mode;
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PTE_SYNC(ptep);
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/*
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* Flush it.
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*/
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(*cf)(cdstp + va_offset, PAGE_SIZE);
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/*
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* Restore the page table entry since we might have interrupted
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* pmap_zero_page or pmap_copy_page which was already using
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* this pte.
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*/
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*ptep = oldpte;
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PTE_SYNC(ptep);
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pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset);
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}
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}
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#endif /* PMAP_CACHE_VIPT */
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@ -3329,7 +3379,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot)
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if (pmap_is_page_colored_p(pg)
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&& ((va ^ pg->mdpage.pvh_attrs) & arm_cache_prefer_mask)) {
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PMAPCOUNT(vac_color_change);
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pmap_flush_page(pg, true);
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pmap_flush_page(pg, PMAP_FLUSH_PRIMARY);
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}
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pg->mdpage.pvh_attrs &= PAGE_SIZE - 1;
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pg->mdpage.pvh_attrs |= PVF_KMPAGE
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|
@ -3687,6 +3737,15 @@ pmap_clear_modify(struct vm_page *pg)
|
|||
|
||||
if (pg->mdpage.pvh_attrs & PVF_MOD) {
|
||||
rv = true;
|
||||
#ifdef PMAP_CACHE_VIPT
|
||||
/*
|
||||
* If we are going to clear the modified bit and there are
|
||||
* no other modified bits set, flush the page to memory and
|
||||
* mark it clean.
|
||||
*/
|
||||
if ((pg->mdpage.pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD)
|
||||
pmap_flush_page(pg, PMAP_CLEAN_PRIMARY);
|
||||
#endif
|
||||
pmap_clearbit(pg, PVF_MOD);
|
||||
} else
|
||||
rv = false;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pmap.h,v 1.89 2008/12/09 20:45:44 pooka Exp $ */
|
||||
/* $NetBSD: pmap.h,v 1.90 2008/12/30 05:51:19 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
|
||||
|
|
@ -122,6 +122,16 @@
|
|||
#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
|
||||
#define L2_SIZE (1 << L2_LOG2)
|
||||
|
||||
/*
|
||||
* tell MI code that the cache is virtually-indexed.
|
||||
* ARMv6 is physically-tagged but all others are virtually-tagged.
|
||||
*/
|
||||
#if ARM_MMU_V6 > 0
|
||||
#define PMAP_CACHE_VIPT
|
||||
#else
|
||||
#define PMAP_CACHE_VIVT
|
||||
#endif
|
||||
|
||||
#ifndef _LOCORE
|
||||
|
||||
struct l1_ttable;
|
||||
|
|
@ -230,8 +240,15 @@ extern pv_addr_t kernel_l1pt;
|
|||
#define PVF_WIRED 0x04 /* mapping is wired */
|
||||
#define PVF_WRITE 0x08 /* mapping is writable */
|
||||
#define PVF_EXEC 0x10 /* mapping is executable */
|
||||
#ifdef PMAP_CACHE_VIVT
|
||||
#define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */
|
||||
#define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */
|
||||
#define PVF_NC (PVF_UNC|PVF_KNC)
|
||||
#endif
|
||||
#ifdef PMAP_CACHE_VIPT
|
||||
#define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */
|
||||
#define PVF_MULTCLR 0x40 /* mapping is multi-colored */
|
||||
#endif
|
||||
#define PVF_COLORED 0x80 /* page has or had a color */
|
||||
#define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */
|
||||
#define PVF_KMPAGE 0x0200 /* page is used for kmem */
|
||||
|
|
@ -239,7 +256,6 @@ extern pv_addr_t kernel_l1pt;
|
|||
#define PVF_KMOD 0x0800 /* unmanaged page is modified */
|
||||
#define PVF_KWRITE (PVF_KENTRY|PVF_WRITE)
|
||||
#define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE)
|
||||
#define PVF_NC (PVF_UNC|PVF_KNC)
|
||||
|
||||
/*
|
||||
* Commonly referenced structures
|
||||
|
|
@ -496,16 +512,6 @@ extern void (*pmap_zero_page_func)(paddr_t);
|
|||
|
||||
/*****************************************************************************/
|
||||
|
||||
/*
|
||||
* tell MI code that the cache is virtually-indexed.
|
||||
* ARMv6 is physically-tagged but all others are virtually-tagged.
|
||||
*/
|
||||
#if ARM_MMU_V6 > 0
|
||||
#define PMAP_CACHE_VIPT
|
||||
#else
|
||||
#define PMAP_CACHE_VIVT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Definitions for MMU domains
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue