Hanlde NMI on microSPARC-IIep.
We don't do much useful except reporting, but that's better than to stupidly use sun4m handler and wedge the machine. May need to revisit what's fatal. Prodding by macallan@
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uwe
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.45 2005/07/10 17:02:19 christos Exp $
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# $NetBSD: genassym.cf,v 1.46 2005/09/10 01:27:54 uwe Exp $
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#
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# Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -198,6 +198,10 @@ define PCIC_SOFT_INTR_CLEAR_REG offsetof(struct msiiep_pcic_reg, pcic_soft_intr_
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define PCIC_SOFT_INTR_SET_REG offsetof(struct msiiep_pcic_reg, pcic_soft_intr_set)
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define PCIC_SCCR_REG offsetof(struct msiiep_pcic_reg, pcic_sccr)
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define PCIC_SYS_ITMR_CLR_REG offsetof(struct msiiep_pcic_reg, pcic_sys_itmr_clr)
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define PCIC_SYS_ITMR_SET_REG offsetof(struct msiiep_pcic_reg, pcic_sys_itmr_set)
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define MSIIEP_SYS_ITMR_ALL MSIIEP_SYS_ITMR_ALL
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# errno
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define EFAULT EFAULT
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define ENAMETOOLONG ENAMETOOLONG
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.87 2005/06/16 04:17:49 briggs Exp $ */
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/* $NetBSD: intr.c,v 1.88 2005/09/10 01:27:54 uwe Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.87 2005/06/16 04:17:49 briggs Exp $");
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.88 2005/09/10 01:27:54 uwe Exp $");
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#include "opt_multiprocessor.h"
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#include "opt_sparc_arch.h"
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@ -202,7 +202,7 @@ softnet(fp)
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#undef DONETISR
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}
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#if defined(SUN4M) || defined(SUN4D)
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#if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D)
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void nmi_hard __P((void));
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void nmi_soft __P((struct trapframe *));
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@ -384,6 +384,105 @@ static void xcallintr(void *v)
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#endif /* MULTIPROCESSOR */
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#endif /* SUN4M || SUN4D */
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#ifdef MSIIEP
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/*
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* It's easier to make this separate so that not to further obscure
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* SUN4M case with more ifdefs. There's no common functionality
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* anyway.
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*/
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#include <sparc/sparc/msiiepreg.h>
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/* ms-IIep PCIC registers are mapped at fixed VA */
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#define mspcic ((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)
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void nmi_hard_msiiep(void);
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void nmi_soft_msiiep(void);
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void
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nmi_hard_msiiep(void)
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{
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uint32_t si;
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int byteswap;
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char bits[128];
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int fatal = 0;
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si = mspcic->pcic_sys_ipr;
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printf("NMI: system interrupts: %s\n",
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bitmask_snprintf(si, MSIIEP_SYS_IPR_BITS, bits, sizeof(bits)));
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if (si & MSIIEP_SYS_IPR_MEM_FAULT) {
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uint32_t afsr, afar, mfsr, mfar;
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afar = *(volatile uint32_t *)MSIIEP_AFAR;
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afsr = *(volatile uint32_t *)MSIIEP_AFSR;
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mfar = *(volatile uint32_t *)MSIIEP_MFAR;
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mfsr = *(volatile uint32_t *)MSIIEP_MFSR;
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if (afsr & MSIIEP_AFSR_ERR)
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printf("async fault: afsr=%s; afar=%08x\n",
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bitmask_snprintf(afsr, MSIIEP_AFSR_BITS,
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bits, sizeof(bits)),
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afar);
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if (mfsr & MSIIEP_MFSR_ERR)
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printf("mem fault: mfsr=%s; mfar=%08x\n",
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bitmask_snprintf(mfsr, MSIIEP_MFSR_BITS,
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bits, sizeof(bits)),
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mfar);
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fatal = 0;
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}
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byteswap = mspcic->pcic_pio_ctrl & MSIIEP_PIO_CTRL_BIG_ENDIAN;
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if (si & MSIIEP_SYS_IPR_SERR) { /* XXX */
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printf("serr#\n");
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fatal = 0;
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}
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if (si & MSIIEP_SYS_IPR_DMA_ERR) {
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uint32_t iotlb_err_addr = mspcic->pcic_iotlb_err_addr;
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if (byteswap)
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iotlb_err_addr = bswap32(iotlb_err_addr);
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printf("dma: %08x\n", iotlb_err_addr);
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fatal = 0;
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}
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if (si & MSIIEP_SYS_IPR_PIO_ERR) {
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uint32_t pio_err_addr = mspcic->pcic_pio_err_addr;
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if (byteswap)
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pio_err_addr = bswap32(pio_err_addr);
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printf("pio: addr=%08x, cmd=%x\n",
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pio_err_addr, mspcic->pcic_pio_err_cmd);
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fatal = 0;
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}
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if (fatal)
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panic("nmi");
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/* Clear the NMI if it was PCIC related */
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mspcic->pcic_sys_ipr_clr = MSIIEP_SYS_IPR_CLR_ALL;
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}
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void
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nmi_soft_msiiep(void)
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{
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panic("soft nmi");
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}
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#endif /* MSIIEP */
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/*
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* Level 15 interrupts are special, and not vectored here.
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* Only `prewired' interrupts appear here; boot-time configured devices
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.216 2005/07/10 17:02:19 christos Exp $ */
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/* $NetBSD: locore.s,v 1.217 2005/09/10 01:27:54 uwe Exp $ */
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/*
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* Copyright (c) 1996 Paul Kranenburg
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@ -3103,6 +3103,8 @@ nmi_sun4m:
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INTR_SETUP(-CCFSZ-80)
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INCR(_C_LABEL(uvmexp)+V_INTR) ! cnt.v_intr++; (clobbers %o0,%o1)
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#if !defined(MSIIEP) /* normal sun4m */
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/* Read the Pending Interrupts register */
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sethi %hi(CPUINFO_VA+CPUINFO_INTREG), %l6
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ld [%l6 + %lo(CPUINFO_VA+CPUINFO_INTREG)], %l6
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@ -3194,8 +3196,69 @@ nmi_sun4m:
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4:
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b return_from_trap
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wr %l4, 0, %y ! restore y
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#else /* MSIIEP*/
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sethi %hi(MSIIEP_PCIC_VA), %l6
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/* Read the Processor Interrupt Pending register */
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ld [%l6 + PCIC_PROC_IPR_REG], %l5
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/*
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* Level 15 interrupts are nonmaskable, so with traps off,
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* disable all interrupts to prevent recursion.
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*/
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set MSIIEP_SYS_ITMR_ALL, %l4
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st %l4, [%l6 + PCIC_SYS_ITMR_SET_REG]
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set (1 << 15), %l4
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btst %l4, %l5 ! has pending level 15 hw intr?
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bz 1f
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nop
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/* hard level 15 interrupt */
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sethi %hi(_C_LABEL(nmi_hard_msiiep)), %o3
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b 2f
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or %o3, %lo(_C_LABEL(nmi_hard_msiiep)), %o3
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1: /* soft level 15 interrupt */
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sth %l4, [%l6 + PCIC_SOFT_INTR_CLEAR_REG]
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set _C_LABEL(nmi_soft_msiiep), %o3
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2:
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/* XXX: call sequence is identical to sun4m case above. merge? */
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or %l0, PSR_PIL, %o4 ! splhigh()
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wr %o4, 0, %psr !
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wr %o4, PSR_ET, %psr ! turn traps on again
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std %g2, [%sp + CCFSZ + 80] ! save g2, g3
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rd %y, %l4 ! save y
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std %g4, [%sp + CCFSZ + 88] ! save g4, g5
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/* Finish stackframe, call C trap handler */
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mov %g1, %l5 ! save g1, g6, g7
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mov %g6, %l6
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call %o3 ! nmi_hard(0) or nmi_soft(&tf)
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mov %g7, %l7
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mov %l5, %g1 ! restore g1 through g7
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ldd [%sp + CCFSZ + 80], %g2
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ldd [%sp + CCFSZ + 88], %g4
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wr %l0, 0, %psr ! re-disable traps
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mov %l6, %g6
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mov %l7, %g7
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! enable interrupts again (safe, we disabled traps again above)
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sethi %hi(MSIIEP_PCIC_VA), %o0
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set MSIIEP_SYS_ITMR_ALL, %o1
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st %o1, [%o0 + PCIC_SYS_ITMR_CLR_REG]
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b return_from_trap
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wr %l4, 0, %y ! restore y
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#endif /* MSIIEP */
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#endif /* SUN4M */
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#ifdef GPROF
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.globl window_of, winof_user
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.globl window_uf, winuf_user, winuf_ok, winuf_invalid
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