Prepare assembly parts for an eventual transition to ELF. Mostly from a

diff from Steve Woodford.
This commit is contained in:
leo 2001-02-09 21:47:45 +00:00
parent f19685fa10
commit 8f10488c29
5 changed files with 769 additions and 804 deletions

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@ -1,4 +1,4 @@
/* $NetBSD: atari_init.c,v 1.52 2001/02/01 08:58:03 leo Exp $ */ /* $NetBSD: atari_init.c,v 1.53 2001/02/09 21:47:45 leo Exp $ */
/* /*
* Copyright (c) 1995 Leo Weppelman * Copyright (c) 1995 Leo Weppelman
@ -514,25 +514,25 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
if (cputype == CPU_68060) { if (cputype == CPU_68060) {
/* XXX: Need the branch cache be cleared? */ /* XXX: Need the branch cache be cleared? */
asm volatile (".word 0x4e7a,0x0002;" asm volatile (".word 0x4e7a,0x0002;"
"orl #0x400000,d0;" "orl #0x400000,%%d0;"
".word 0x4e7b,0x0002" : : : "d0"); ".word 0x4e7b,0x0002" : : : "d0");
} }
asm volatile ("movel %0,a0;" asm volatile ("movel %0,%%a0;"
".word 0x4e7b,0x8807" : : "a" (Sysseg_pa) : "a0"); ".word 0x4e7b,0x8807" : : "a" (Sysseg_pa) : "a0");
asm volatile (".word 0xf518" : : ); asm volatile (".word 0xf518" : : );
asm volatile ("movel #0xc000,d0;" asm volatile ("movel #0xc000,%%d0;"
".word 0x4e7b,0x0003" : : : "d0" ); ".word 0x4e7b,0x0003" : : : "d0" );
} else } else
#endif #endif
{ {
asm volatile ("pmove %0@,srp" : : "a" (&protorp[0])); asm volatile ("pmove %0@,%%srp" : : "a" (&protorp[0]));
/* /*
* setup and load TC register. * setup and load TC register.
* enable_cpr, enable_srp, pagesize=8k, * enable_cpr, enable_srp, pagesize=8k,
* A = 8 bits, B = 11 bits * A = 8 bits, B = 11 bits
*/ */
tc = 0x82d08b00; tc = 0x82d08b00;
asm volatile ("pmove %0@,tc" : : "a" (&tc)); asm volatile ("pmove %0@,%%tc" : : "a" (&tc));
} }
/* Is this to fool the optimizer?? */ /* Is this to fool the optimizer?? */
@ -995,7 +995,7 @@ initcpu()
extern trapfun illinst; extern trapfun illinst;
#endif #endif
asm volatile ("movl %0,d0; .word 0x4e7b,0x0808" : : asm volatile ("movl %0,%%d0; .word 0x4e7b,0x0808" : :
"d"(m68060_pcr_init):"d0" ); "d"(m68060_pcr_init):"d0" );
/* bus/addrerr vectors */ /* bus/addrerr vectors */

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@ -1,4 +1,4 @@
/* $NetBSD: fpu.c,v 1.6 1997/04/24 22:37:11 gwr Exp $ */ /* $NetBSD: fpu.c,v 1.7 2001/02/09 21:47:46 leo Exp $ */
/*- /*-
* Copyright (c) 1996 The NetBSD Foundation, Inc. * Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -116,7 +116,7 @@ fpu_probe()
* have if this will. We save the state in order to get the * have if this will. We save the state in order to get the
* size of the frame. * size of the frame.
*/ */
asm("movl %0, a0; fsave a0@" : : "a" (&fpframe) : "a0" ); asm("movl %0, %%a0; fsave %%a0@" : : "a" (&fpframe) : "a0" );
b = fpframe.fpf_fsize; b = fpframe.fpf_fsize;

File diff suppressed because it is too large Load Diff

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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.105 2001/01/15 20:19:53 thorpej Exp $ */ /* $NetBSD: machdep.c,v 1.106 2001/02/09 21:47:46 leo Exp $ */
/* /*
* Copyright (c) 1988 University of Utah. * Copyright (c) 1988 University of Utah.
@ -67,6 +67,10 @@
#include <sys/mount.h> #include <sys/mount.h>
#include <sys/syscallargs.h> #include <sys/syscallargs.h>
#if defined(DDB) && defined(__ELF__)
#include <sys/exec_elf.h>
#endif
#include <net/netisr.h> #include <net/netisr.h>
#undef PS /* XXX netccitt/pk.h conflict with machine/reg.h? */ #undef PS /* XXX netccitt/pk.h conflict with machine/reg.h? */
@ -157,7 +161,12 @@ consinit()
extern int end; extern int end;
extern int *esym; extern int *esym;
#ifndef __ELF__
ddb_init(*(int *)&end, ((int *)&end) + 1, esym); ddb_init(*(int *)&end, ((int *)&end) + 1, esym);
#else
ddb_init((int)esym - (int)&end - sizeof(Elf32_Ehdr),
(void *)&end, esym);
#endif
} }
if(boothowto & RB_KDB) if(boothowto & RB_KDB)
Debugger(); Debugger();
@ -389,7 +398,7 @@ identifycpu()
char cputxt[30]; char cputxt[30];
asm(".word 0x4e7a,0x0808;" asm(".word 0x4e7a,0x0808;"
"movl d0,%0" : "=d"(pcr) : : "d0"); "movl %%d0,%0" : "=d"(pcr) : : "d0");
sprintf(cputxt, "68%s060 rev.%d", sprintf(cputxt, "68%s060 rev.%d",
pcr & 0x10000 ? "LC/EC" : "", (pcr>>8)&0xff); pcr & 0x10000 ? "LC/EC" : "", (pcr>>8)&0xff);
cpu = cputxt; cpu = cputxt;

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@ -1,4 +1,4 @@
/* $NetBSD: vectors.s,v 1.13 1998/10/18 04:42:37 itohy Exp $ */ /* $NetBSD: vectors.s,v 1.14 2001/02/09 21:47:46 leo Exp $ */
/* /*
* Copyright (c) 1988 University of Utah * Copyright (c) 1988 University of Utah
@ -36,173 +36,162 @@
* @(#)vectors.s 7.2 (Berkeley) 5/7/91 * @(#)vectors.s 7.2 (Berkeley) 5/7/91
*/ */
.data .data
.globl _buserr,_addrerr GLOBAL(vectab)
.globl _illinst,_zerodiv,_chkinst,_trapvinst,_privinst,_trace
.globl _badtrap
.globl _spurintr,_lev1intr,_lev2intr,_lev3intr
.globl _lev4intr,_lev5intr,_lev6intr,_lev7intr
.globl _trap0
#ifdef COMPAT_13
.globl _trap1
#endif
.globl _trap2,_trap15
.globl _fpfline, _fpunsupp, _fpfault
.globl _trap12, _badmfpint
.globl _vectab, _autovects, _uservects
_vectab:
.long 0x4ef80400 | 0: jmp 0x400:w (unused reset SSP) .long 0x4ef80400 | 0: jmp 0x400:w (unused reset SSP)
.long 0 | 1: NOT USED (reset PC) .long 0 | 1: NOT USED (reset PC)
.long _buserr | 2: bus error VECTOR(buserr) | 2: bus error
.long _addrerr | 3: address error VECTOR(addrerr) | 3: address error
.long _illinst | 4: illegal instruction VECTOR(illinst) | 4: illegal instruction
.long _zerodiv | 5: zero divide VECTOR(zerodiv) | 5: zero divide
.long _chkinst | 6: CHK instruction VECTOR(chkinst) | 6: CHK instruction
.long _trapvinst | 7: TRAPV instruction VECTOR(trapvinst) | 7: TRAPV instruction
.long _privinst | 8: privilege violation VECTOR(privinst) | 8: privilege violation
.long _trace | 9: trace VECTOR(trace) | 9: trace
.long _illinst | 10: line 1010 emulator VECTOR(illinst) | 10: line 1010 emulator
.long _fpfline | 11: line 1111 emulator VECTOR(fpfline) | 11: line 1111 emulator
.long _badtrap | 12: unassigned, reserved VECTOR(badtrap) | 12: unassigned, reserved
.long _coperr | 13: coprocessor protocol violation VECTOR(coperr) | 13: coprocessor protocol violation
.long _fmterr | 14: format error VECTOR(fmterr) | 14: format error
.long _badtrap | 15: uninitialized interrupt vector VECTOR(badtrap) | 15: uninitialized interrupt vector
.long _badtrap | 16: unassigned, reserved VECTOR(badtrap) | 16: unassigned, reserved
.long _badtrap | 17: unassigned, reserved VECTOR(badtrap) | 17: unassigned, reserved
.long _badtrap | 18: unassigned, reserved VECTOR(badtrap) | 18: unassigned, reserved
.long _badtrap | 19: unassigned, reserved VECTOR(badtrap) | 19: unassigned, reserved
.long _badtrap | 20: unassigned, reserved VECTOR(badtrap) | 20: unassigned, reserved
.long _badtrap | 21: unassigned, reserved VECTOR(badtrap) | 21: unassigned, reserved
.long _badtrap | 22: unassigned, reserved VECTOR(badtrap) | 22: unassigned, reserved
.long _badtrap | 23: unassigned, reserved VECTOR(badtrap) | 23: unassigned, reserved
.long _spurintr | 24: spurious interrupt VECTOR(spurintr) | 24: spurious interrupt
_autovects:
.long _lev1intr | 25: level 1 interrupt autovector GLOBAL(autovects)
.long _lev2intr | 26: level 2 interrupt autovector VECTOR(lev1intr) | 25: level 1 interrupt autovector
.long _lev3intr | 27: level 3 interrupt autovector VECTOR(lev2intr) | 26: level 2 interrupt autovector
.long _lev4intr | 28: level 4 interrupt autovector VECTOR(lev3intr) | 27: level 3 interrupt autovector
.long _lev5intr | 29: level 5 interrupt autovector VECTOR(lev4intr) | 28: level 4 interrupt autovector
.long _lev6intr | 30: level 6 interrupt autovector VECTOR(lev5intr) | 29: level 5 interrupt autovector
.long _lev7intr | 31: level 7 interrupt autovector VECTOR(lev6intr) | 30: level 6 interrupt autovector
.long _trap0 | 32: syscalls VECTOR(lev7intr) | 31: level 7 interrupt autovector
VECTOR(trap0) | 32: syscalls
#ifdef COMPAT_13 #ifdef COMPAT_13
.long _trap1 | 33: compat_13_sigreturn VECTOR(trap1) | 33: compat_13_sigreturn
#else #else
.long _illinst VECTOR(illinst
#endif #endif
.long _trap2 | 34: trace VECTOR(trap2) | 34: trace
.long _trap3 | 35: sigreturn special syscall VECTOR(trap3) | 35: sigreturn special syscall
.long _illinst | 36: TRAP instruction vector VECTOR(illinst) | 36: TRAP instruction vector
.long _illinst | 37: TRAP instruction vector VECTOR(illinst) | 37: TRAP instruction vector
.long _illinst | 38: TRAP instruction vector VECTOR(illinst) | 38: TRAP instruction vector
.long _illinst | 39: TRAP instruction vector VECTOR(illinst) | 39: TRAP instruction vector
.long _illinst | 40: TRAP instruction vector VECTOR(illinst) | 40: TRAP instruction vector
.long _illinst | 41: TRAP instruction vector VECTOR(illinst) | 41: TRAP instruction vector
.long _illinst | 42: TRAP instruction vector VECTOR(illinst) | 42: TRAP instruction vector
.long _illinst | 43: TRAP instruction vector VECTOR(illinst) | 43: TRAP instruction vector
.long _trap12 | 44: TRAP instruction vector VECTOR(trap12) | 44: TRAP instruction vector
.long _illinst | 45: TRAP instruction vector VECTOR(illinst) | 45: TRAP instruction vector
.long _illinst | 46: TRAP instruction vector VECTOR(illinst) | 46: TRAP instruction vector
.long _trap15 | 47: TRAP instruction vector VECTOR(trap15) | 47: TRAP instruction vector
#ifdef FPSP #ifdef FPSP
.globl bsun, inex, dz, unfl, operr, ovfl, snan ASVECTOR(bsun) | 48: FPCP branch/set on unordered cond
.long bsun | 48: FPCP branch/set on unordered cond ASVECTOR(inex) | 49: FPCP inexact result
.long inex | 49: FPCP inexact result ASVECTOR(dz) | 50: FPCP divide by zero
.long dz | 50: FPCP divide by zero ASVECTOR(unfl) | 51: FPCP underflow
.long unfl | 51: FPCP underflow ASVECTOR(operr) | 52: FPCP operand error
.long operr | 52: FPCP operand error ASVECTOR(ovfl) | 53: FPCP overflow
.long ovfl | 53: FPCP overflow ASVECTOR(snan) | 54: FPCP signalling NAN
.long snan | 54: FPCP signalling NAN
#else #else
.globl _fpfault VECTOR(fpfault) | 48: FPCP branch/set on unordered cond
.long _fpfault | 48: FPCP branch/set on unordered cond VECTOR(fpfault) | 49: FPCP inexact result
.long _fpfault | 49: FPCP inexact result VECTOR(fpfault) | 50: FPCP divide by zero
.long _fpfault | 50: FPCP divide by zero VECTOR(fpfault) | 51: FPCP underflow
.long _fpfault | 51: FPCP underflow VECTOR(fpfault) | 52: FPCP operand error
.long _fpfault | 52: FPCP operand error VECTOR(fpfault) | 53: FPCP overflow
.long _fpfault | 53: FPCP overflow VECTOR(fpfault) | 54: FPCP signalling NAN
.long _fpfault | 54: FPCP signalling NAN
#endif #endif
.long _fpunsupp | 55: FPCP unimplemented data type VECTOR(fpunsupp) | 55: FPCP unimplemented data type
.long _badtrap | 56: unassigned, reserved VECTOR(badtrap) | 56: unassigned, reserved
.long _badtrap | 57: unassigned, reserved VECTOR(badtrap) | 57: unassigned, reserved
.long _badtrap | 58: unassigned, reserved VECTOR(badtrap) | 58: unassigned, reserved
.long _badtrap | 59: unassigned, reserved VECTOR(badtrap) | 59: unassigned, reserved
.long _badtrap | 60: unassigned, reserved VECTOR(badtrap) | 60: unassigned, reserved
.long _badtrap | 61: unassigned, reserved VECTOR(badtrap) | 61: unassigned, reserved
.long _badtrap | 62: unassigned, reserved VECTOR(badtrap) | 62: unassigned, reserved
.long _badtrap | 63: unassigned, reserved VECTOR(badtrap) | 63: unassigned, reserved
_uservects: GLOBAL(uservects)
/* /*
* MFP 1 auto vectors (ipl 6) * MFP 1 auto vectors (ipl 6)
*/ */
.long _intr_glue | 64: parallel port - BUSY VECTOR(intr_glue) | 64: parallel port - BUSY
.long _badmfpint | 65: modem port 1 - DCD VECTOR(badmfpint) | 65: modem port 1 - DCD
.long _badmfpint | 66: modem port 1 - CTS VECTOR(badmfpint) | 66: modem port 1 - CTS
.long _badmfpint | 67: ISA1 [ Hades only ] VECTOR(badmfpint) | 67: ISA1 [ Hades only ]
.long _badmfpint | 68: modem port 1 baudgen (Timer D) VECTOR(badmfpint) | 68: modem port 1 baudgen (Timer D)
#ifdef STATCLOCK #ifdef STATCLOCK
.long mfp_timc | 69: Timer C {stat,prof}clock ASVECTOR(mfp_timc) | 69: Timer C {stat,prof}clock
#else #else
.long _badmfpint | 69: Timer C VECTOR(badmfpint) | 69: Timer C
#endif /* STATCLOCK */ #endif /* STATCLOCK */
.long mfp_kbd | 70: KBD/MIDI IRQ ASVECTOR(mfp_kbd) | 70: KBD/MIDI IRQ
.long _intr_glue | 71: FDC/ACSI DMA VECTOR(intr_glue) | 71: FDC/ACSI DMA
.long _badmfpint | 72: Display enable counter VECTOR(badmfpint) | 72: Display enable counter
.long _badmfpint | 73: modem port 1 - XMIT error VECTOR(badmfpint) | 73: modem port 1 - XMIT error
.long _badmfpint | 74: modem port 1 - XMIT buffer empty VECTOR(badmfpint) | 74: modem port 1 - XMIT buffer empty
.long _badmfpint | 75: modem port 1 - RCV error VECTOR(badmfpint) | 75: modem port 1 - RCV error
.long _badmfpint | 76: modem port 1 - RCV buffer full VECTOR(badmfpint) | 76: modem port 1 - RCV buffer full
.long mfp_tima | 77: Timer A (System clock) ASVECTOR(mfp_tima) | 77: Timer A (System clock)
.long _badmfpint | 78: modem port 1 - RI VECTOR(badmfpint) | 78: modem port 1 - RI
.long _badmfpint | 79: Monochrome detect (ISA2 [ Hades only ]) VECTOR(badmfpint) | 79: Monochrome detect (ISA2 [ Hades only ])
/* /*
* MFP 2 auto vectors (ipl 6) * MFP 2 auto vectors (ipl 6)
*/ */
.long _badmfpint | 80: I/O pin 1 J602 VECTOR(badmfpint) | 80: I/O pin 1 J602
.long _badmfpint | 81: I/O pin 3 J602 VECTOR(badmfpint) | 81: I/O pin 3 J602
.long _badmfpint | 82: SCC-DMA VECTOR(badmfpint) | 82: SCC-DMA
.long _badmfpint | 83: modem port 2 - RI VECTOR(badmfpint) | 83: modem port 2 - RI
.long _badmfpint | 84: serial port 1 baudgen (Timer D) VECTOR(badmfpint) | 84: serial port 1 baudgen (Timer D)
.long _badmfpint | 85: TCCLC SCC (Timer C) VECTOR(badmfpint) | 85: TCCLC SCC (Timer C)
.long _badmfpint | 86: FDC Drive Ready VECTOR(badmfpint) | 86: FDC Drive Ready
.long mfp2_5380dm | 87: SCSI DMA ASVECTOR(mfp2_5380dm) | 87: SCSI DMA
.long _badmfpint | 88: Display enable (Timer B) VECTOR(badmfpint) | 88: Display enable (Timer B)
.long _badmfpint | 89: serial port 1 - XMIT error VECTOR(badmfpint) | 89: serial port 1 - XMIT error
.long _badmfpint | 90: serial port 1 - XMIT buffer empty VECTOR(badmfpint) | 90: serial port 1 - XMIT buffer empty
.long _badmfpint | 91: serial port 1 - RCV error VECTOR(badmfpint) | 91: serial port 1 - RCV error
.long _badmfpint | 92: serial port 1 - RCV buffer full VECTOR(badmfpint) | 92: serial port 1 - RCV buffer full
.long _badmfpint | 93: Timer A VECTOR(badmfpint) | 93: Timer A
.long _badmfpint | 94: RTC VECTOR(badmfpint) | 94: RTC
.long mfp2_5380 | 95: SCSI 5380 ASVECTOR(mfp2_5380) | 95: SCSI 5380
/* /*
* Interrupts from the 8530 SCC * Interrupts from the 8530 SCC
*/ */
.long sccint | 96: SCC Tx empty channel B ASVECTOR(sccint) | 96: SCC Tx empty channel B
.long _badtrap | 97: Not used VECTOR(badtrap) | 97: Not used
.long sccint | 98: SCC Ext./Status Channel B ASVECTOR(sccint) | 98: SCC Ext./Status Channel B
.long _badtrap | 99: Not used VECTOR(badtrap) | 99: Not used
.long sccint | 100: SCC Rx Channel B ASVECTOR(sccint) | 100: SCC Rx Channel B
.long _badtrap | 101: Not used VECTOR(badtrap) | 101: Not used
.long sccint | 102: SCC Special Rx cond. Channel B ASVECTOR(sccint) | 102: SCC Special Rx cond. Channel B
.long _badtrap | 103: Not used VECTOR(badtrap) | 103: Not used
.long sccint | 104: SCC Tx empty channel A ASVECTOR(sccint) | 104: SCC Tx empty channel A
.long _badtrap | 105: Not used VECTOR(badtrap) | 105: Not used
.long sccint | 106: SCC Ext./Status Channel A ASVECTOR(sccint) | 106: SCC Ext./Status Channel A
.long _badtrap | 107: Not used VECTOR(badtrap) | 107: Not used
.long sccint | 108: SCC Rx Channel A ASVECTOR(sccint) | 108: SCC Rx Channel A
.long _badtrap | 109: Not used VECTOR(badtrap) | 109: Not used
.long sccint | 110: SCC Special Rx cond. Channel A ASVECTOR(sccint) | 110: SCC Special Rx cond. Channel A
.long _badtrap | 111: Not used VECTOR(badtrap) | 111: Not used
#define BADTRAP16 .long _badtrap,_badtrap,_badtrap,_badtrap,\ #define BADTRAP16 VECTOR(badtrap) ; VECTOR(badtrap) ; \
_badtrap,_badtrap,_badtrap,_badtrap,\ VECTOR(badtrap) ; VECTOR(badtrap) ; \
_badtrap,_badtrap,_badtrap,_badtrap,\ VECTOR(badtrap) ; VECTOR(badtrap) ; \
_badtrap,_badtrap,_badtrap,_badtrap VECTOR(badtrap) ; VECTOR(badtrap) ; \
VECTOR(badtrap) ; VECTOR(badtrap) ; \
VECTOR(badtrap) ; VECTOR(badtrap) ; \
VECTOR(badtrap) ; VECTOR(badtrap) ; \
VECTOR(badtrap) ; VECTOR(badtrap) ;
BADTRAP16 | 112-255: user interrupt vectors BADTRAP16 | 112-255: user interrupt vectors
BADTRAP16 | 112-255: user interrupt vectors BADTRAP16 | 112-255: user interrupt vectors
BADTRAP16 | 112-255: user interrupt vectors BADTRAP16 | 112-255: user interrupt vectors