Make sure some registers are accessed in 16-bit mode.
This commit is contained in:
mycroft
parent
3441f118d5
commit
8ee41dc35a
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@ -1,4 +1,4 @@
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/* $NetBSD: vm86.c,v 1.2 1996/01/08 19:11:00 mycroft Exp $ */
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/* $NetBSD: vm86.c,v 1.3 1996/01/08 22:23:35 mycroft Exp $ */
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/*
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* Copyright (c) 1995 John T. Kohl
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@ -70,18 +70,9 @@ static void fast_intxx __P((struct proc *, int));
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#define SETDIRECT ((~(PSL_USERSTATIC|PSL_NT)) & 0xffff)
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#define GETDIRECT (SETDIRECT|0x02a) /* add in two MBZ bits */
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#define IP(tf) (*(u_short *)&tf->tf_eip)
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#define SP(tf) (*(u_short *)&tf->tf_esp)
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/*
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* Boy are these ugly, but we need to do the correct 16-bit arithmetic.
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* Gcc makes a mess of it, so we do it inline and use non-obvious calling
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* conventions..
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*/
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#define putbyte(base, ptr, val) \
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__asm__ __volatile__( \
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"decw %w0\n\t" \
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"movb %2,0(%1,%0)" \
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: "=r" (ptr) \
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: "r" (base), "q" (val), "0" (ptr))
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#define putword(base, ptr, val) \
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__asm__ __volatile__( \
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@ -94,13 +85,13 @@ __asm__ __volatile__( \
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#define putdword(base, ptr, val) \
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__asm__ __volatile__( \
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"decw %w0\n\t" \
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"rorl $16,%2\n\t" \
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"decw %w0\n\t" \
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"movb %h2,0(%1,%0)\n\t" \
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"decw %w0\n\t" \
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"movb %b2,0(%1,%0)\n\t" \
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"decw %w0\n\t" \
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"rorl $16,%2\n\t" \
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"decw %w0\n\t" \
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"movb %h2,0(%1,%0)\n\t" \
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"decw %w0\n\t" \
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"movb %b2,0(%1,%0)" \
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@ -230,10 +221,9 @@ fast_intxx(p, intrno)
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*/
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struct vm86_struct *u_vm86p;
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struct { u_short ip, cs; } ihand;
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struct { u_short short1, short2, short3; } threeshorts;
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u_short cs;
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u_long ss;
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u_long ss, sp;
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/*
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* Note: u_vm86p points to user-space, we only compute offsets
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@ -274,13 +264,14 @@ fast_intxx(p, intrno)
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* simulate direct INT call.
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*/
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ss = tf->tf_ss << 4;
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tf->tf_esp &= 0xffff;
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sp = SP(tf);
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putword(ss, tf->tf_esp, get_vflags(p));
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putword(ss, tf->tf_esp, tf->tf_cs);
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putword(ss, tf->tf_esp, tf->tf_eip);
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putword(ss, sp, get_vflags(p));
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putword(ss, sp, tf->tf_cs);
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putword(ss, sp, IP(tf));
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SP(tf) = sp;
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tf->tf_eip = ihand.ip;
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IP(tf) = ihand.ip;
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tf->tf_cs = ihand.cs;
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/* disable further "hardware" interrupts, turn off any tracing. */
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@ -345,18 +336,21 @@ vm86_gpfault(p, type)
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* address space for checking. remember that the frame's
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* segment selectors are real-mode style selectors.
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*/
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u_long cs, ss;
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u_char tmpbyte;
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u_long cs, ip, ss, sp;
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cs = tf->tf_cs << 4;
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tf->tf_eip &= 0xffff;
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ip = IP(tf);
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ss = tf->tf_ss << 4;
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tf->tf_esp &= 0xffff;
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sp = SP(tf);
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/*
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* For most of these, we must set all the registers before calling
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* macros/functions which might do a return_to_32bit.
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*/
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switch (getbyte(cs, tf->tf_eip)) {
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tmpbyte = getbyte(cs, ip);
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IP(tf) = ip;
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switch (tmpbyte) {
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case CLI:
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/* simulate handling of IF */
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VM86_EFLAGS(p) &= ~PSL_VIF;
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@ -373,42 +367,50 @@ vm86_gpfault(p, type)
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case INTxx:
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/* try fast intxx, or return to 32bit mode to handle it. */
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fast_intxx(p, getbyte(cs, tf->tf_eip));
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tmpbyte = getbyte(cs, ip);
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IP(tf) = ip;
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fast_intxx(p, tmpbyte);
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break;
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case PUSHF:
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putword(ss, tf->tf_esp, get_vflags(p));
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putword(ss, sp, get_vflags(p));
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SP(tf) = sp;
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break;
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case IRET:
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tf->tf_eip = getword(ss, tf->tf_esp);
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tf->tf_cs = getword(ss, tf->tf_esp);
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IP(tf) = getword(ss, sp);
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tf->tf_cs = getword(ss, sp);
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case POPF:
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set_vflags_short(p, getword(ss, tf->tf_esp));
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set_vflags_short(p, getword(ss, sp));
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SP(tf) = sp;
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break;
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case OPSIZ:
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switch (getbyte(cs, tf->tf_eip)) {
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tmpbyte = getbyte(cs, ip);
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IP(tf) = ip;
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switch (tmpbyte) {
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case PUSHF:
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putdword(ss, tf->tf_esp, get_vflags(p));
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putdword(ss, sp, get_vflags(p));
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SP(tf) = sp;
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break;
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case IRET:
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tf->tf_eip = getdword(ss, tf->tf_esp);
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tf->tf_cs = getdword(ss, tf->tf_esp);
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IP(tf) = getdword(ss, sp);
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tf->tf_cs = getdword(ss, sp);
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case POPF:
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set_vflags(p, getdword(ss, tf->tf_esp));
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set_vflags(p, getdword(ss, sp));
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SP(tf) = sp;
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break;
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default:
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tf->tf_eip -= 2;
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IP(tf) -= 2;
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goto bad;
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}
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break;
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case LOCK:
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default:
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tf->tf_eip -= 1;
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IP(tf) -= 1;
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goto bad;
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}
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return;
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@ -426,7 +428,7 @@ i386_vm86(p, args, retval)
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{
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struct trapframe *tf = p->p_md.md_regs;
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struct vm86_kern vm86s;
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int psl, err;
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int err;
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if (err = copyin(args, &vm86s, sizeof(vm86s)))
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return err;
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