From 8e8cc5afced64f769fdd4f2f1268c24d02d74e04 Mon Sep 17 00:00:00 2001 From: tsutsui Date: Thu, 10 Mar 2011 17:05:41 +0000 Subject: [PATCH] Set correct struct clockframe .intr value for hardclock(9). --- sys/arch/ews4800mips/ews4800mips/tr2_intr.c | 6 +++--- sys/arch/ews4800mips/ews4800mips/tr2a_intr.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/sys/arch/ews4800mips/ews4800mips/tr2_intr.c b/sys/arch/ews4800mips/ews4800mips/tr2_intr.c index 9136ed9d415c..48af3a0f855d 100644 --- a/sys/arch/ews4800mips/ews4800mips/tr2_intr.c +++ b/sys/arch/ews4800mips/ews4800mips/tr2_intr.c @@ -1,4 +1,4 @@ -/* $NetBSD: tr2_intr.c,v 1.11 2011/02/20 07:55:20 matt Exp $ */ +/* $NetBSD: tr2_intr.c,v 1.12 2011/03/10 17:05:41 tsutsui Exp $ */ /*- * Copyright (c) 2004, 2005 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.11 2011/02/20 07:55:20 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.12 2011/03/10 17:05:41 tsutsui Exp $"); #define __INTR_PRIVATE #include @@ -154,7 +154,7 @@ tr2_intr(int ppl, vaddr_t pc, uint32_t status) if (ipending & MIPS_INT_MASK_5) { /* CLOCK */ cf.pc = pc; cf.sr = status; - cf.intr = (curcpu()->ci_idepth > 0); + cf.intr = (curcpu()->ci_idepth > 1); *PICNIC_INT5_STATUS_REG = 0; r = *PICNIC_INT5_STATUS_REG; diff --git a/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c b/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c index 044077ae6b84..d03dc0b4f095 100644 --- a/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c +++ b/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c @@ -1,4 +1,4 @@ -/* $NetBSD: tr2a_intr.c,v 1.14 2011/02/24 14:40:43 tsutsui Exp $ */ +/* $NetBSD: tr2a_intr.c,v 1.15 2011/03/10 17:05:41 tsutsui Exp $ */ /*- * Copyright (c) 2004, 2005 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.14 2011/02/24 14:40:43 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.15 2011/03/10 17:05:41 tsutsui Exp $"); #define __INTR_PRIVATE #include @@ -183,7 +183,7 @@ tr2a_intr(int ppl, vaddr_t pc, uint32_t status) if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) { cf.pc = pc; cf.sr = status; - cf.intr = (curcpu()->ci_idepth > 0); + cf.intr = (curcpu()->ci_idepth > 1); tr2a_wbflush(); *INTC_CLEAR_REG = 0x7c; *INTC_STATUS_REG;