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Make this compile.

This commit is contained in:
tsubai 1999-06-20 05:42:09 +00:00
parent 8c3bc73ea2
commit 8d68bdec13
1 changed files with 13 additions and 1 deletions
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14
sys/arch/newsmips/newsmips/locore_machdep.S
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@ -1,4 +1,4 @@
/* $NetBSD: locore_machdep.S,v 1.4 1998/09/11 17:37:46 jonathan Exp $ */
/* $NetBSD: locore_machdep.S,v 1.5 1999/06/20 05:42:09 tsubai Exp $ */
/*
* Copyright (c) 1992, 1993
@ -170,6 +170,18 @@ LEAF(splsoftnet)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(splsoftnet)
/*
* nesting interrupt masks.
*/
#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
/*
* hardware-level spls for hardware where the device interrupt priorites
* are ordered, and map onto mips interrupt pins in increasing priority.