Chip detection and MP spinup code for Tegra210
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jmcneill
parent
ea56b0245d
commit
8c41086dcf
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# $NetBSD: files.tegra,v 1.35 2017/04/29 11:01:51 jmcneill Exp $
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# $NetBSD: files.tegra,v 1.36 2017/05/25 23:26:48 jmcneill Exp $
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#
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# Configuration info for NVIDIA Tegra ARM Peripherals
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#
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@ -27,6 +27,9 @@ device tegra124cpu
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attach tegra124cpu at fdt with tegra124_cpu
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file arch/arm/nvidia/tegra124_cpu.c tegra124_cpu
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# Tegra T210 (X1) support
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file arch/arm/nvidia/soc_tegra210.c soc_tegra210
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# Interrupt controller
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device tegralic
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attach tegralic at fdt with tegra_lic
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@ -161,4 +164,6 @@ defparam opt_tegra.h MEMSIZE
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# SOC parameters
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defflag opt_tegra.h SOC_TEGRAK1
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defflag opt_tegra.h SOC_TEGRAX1
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defflag opt_tegra.h SOC_TEGRA124: SOC_TEGRAK1
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defflag opt_tegra.h SOC_TEGRA210: SOC_TEGRAX1
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@ -0,0 +1,81 @@
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/* $NetBSD: soc_tegra210.c,v 1.1 2017/05/25 23:26:48 jmcneill Exp $ */
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/*-
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* Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_tegra.h"
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#include "opt_multiprocessor.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: soc_tegra210.c,v 1.1 2017/05/25 23:26:48 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <dev/fdt/fdtvar.h>
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#include <arm/cpufunc.h>
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#include <arm/nvidia/tegra_reg.h>
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#include <arm/nvidia/tegra_pmcreg.h>
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#include <arm/nvidia/tegra_var.h>
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#define EVP_RESET_VECTOR_0_REG 0x100
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void
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tegra210_mpinit(void)
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{
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#if defined(MULTIPROCESSOR)
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extern void cortex_mpstart(void);
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bus_space_tag_t bst = &armv7_generic_bs_tag;
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bus_space_handle_t bsh;
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bus_space_subregion(bst, tegra_ppsb_bsh,
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TEGRA_EVP_OFFSET, TEGRA_EVP_SIZE, &bsh);
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arm_cpu_max = 4;
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bus_space_write_4(bst, bsh, EVP_RESET_VECTOR_0_REG,
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(uint32_t)cortex_mpstart);
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bus_space_barrier(bst, bsh, EVP_RESET_VECTOR_0_REG, 4,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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uint32_t started = 0;
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tegra_pmc_power(PMC_PARTID_CPU1, true); started |= __BIT(1);
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tegra_pmc_power(PMC_PARTID_CPU2, true); started |= __BIT(2);
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tegra_pmc_power(PMC_PARTID_CPU3, true); started |= __BIT(3);
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for (u_int i = 0x10000000; i > 0; i--) {
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arm_dmb();
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if (arm_cpu_hatched == started)
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break;
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}
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#endif
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_soc.c,v 1.10 2017/04/22 23:53:24 jmcneill Exp $ */
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/* $NetBSD: tegra_soc.c,v 1.11 2017/05/25 23:26:48 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -30,7 +30,7 @@
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#include "opt_multiprocessor.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.10 2017/04/22 23:53:24 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.11 2017/05/25 23:26:48 jmcneill Exp $");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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@ -98,6 +98,11 @@ tegra_mpinit(void)
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case CHIP_ID_TEGRA124:
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tegra124_mpinit();
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break;
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#endif
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#ifdef SOC_TEGRA210
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case CHIP_ID_TEGRA210:
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tegra210_mpinit();
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break;
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#endif
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default:
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panic("Unsupported SOC ID %#x", tegra_chip_id());
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@ -127,6 +132,7 @@ tegra_chip_name(void)
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switch (tegra_chip_id()) {
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case CHIP_ID_TEGRA124: return "Tegra K1 (T124)";
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case CHIP_ID_TEGRA132: return "Tegra K1 (T132)";
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case CHIP_ID_TEGRA210: return "Tegra X1 (T210)";
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default: return "Unknown Tegra SoC";
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_var.h,v 1.34 2017/05/25 23:12:59 jmcneill Exp $ */
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/* $NetBSD: tegra_var.h,v 1.35 2017/05/25 23:26:48 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -107,6 +107,9 @@ void tegra_cpufreq_register(const struct tegra_cpufreq_func *);
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#if defined(SOC_TEGRA124)
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void tegra124_mpinit(void);
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#endif
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#if defined(SOC_TEGRA210)
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void tegra210_mpinit(void);
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#endif
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static void inline
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tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
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