Add a basic driver for the Clock and Reset controller, use it to determine
CPU frequency.
This commit is contained in:
jmcneill
parent
9521ae7bfd
commit
8bcb30da14
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@ -1,4 +1,4 @@
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# $NetBSD: files.tegra,v 1.2 2015/03/29 22:27:04 jmcneill Exp $
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# $NetBSD: files.tegra,v 1.3 2015/04/28 11:15:55 jmcneill Exp $
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#
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# Configuration info for NVIDIA Tegra ARM Peripherals
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#
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@ -31,6 +31,11 @@ device tegrapmc
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attach tegrapmc at tegraio with tegra_pmc
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file arch/arm/nvidia/tegra_pmc.c tegra_pmc
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# Clock and Reset controller
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device tegracar
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attach tegracar at tegraio with tegra_car
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file arch/arm/nvidia/tegra_car.c tegra_car
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# UART
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attach com at tegraio with tegra_com
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file arch/arm/nvidia/tegra_com.c tegra_com needs-flag
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@ -0,0 +1,123 @@
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/* $NetBSD: tegra_car.c,v 1.1 2015/04/28 11:15:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "locators.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.1 2015/04/28 11:15:55 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <arm/nvidia/tegra_reg.h>
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#include <arm/nvidia/tegra_carreg.h>
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#include <arm/nvidia/tegra_var.h>
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static int tegra_car_match(device_t, cfdata_t, void *);
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static void tegra_car_attach(device_t, device_t, void *);
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struct tegra_car_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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};
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static struct tegra_car_softc *pmc_softc = NULL;
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CFATTACH_DECL_NEW(tegra_car, sizeof(struct tegra_car_softc),
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tegra_car_match, tegra_car_attach, NULL, NULL);
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static int
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tegra_car_match(device_t parent, cfdata_t cf, void *aux)
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{
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return 1;
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}
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static void
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tegra_car_attach(device_t parent, device_t self, void *aux)
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{
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struct tegra_car_softc * const sc = device_private(self);
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struct tegraio_attach_args * const tio = aux;
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const struct tegra_locators * const loc = &tio->tio_loc;
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sc->sc_dev = self;
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sc->sc_bst = tio->tio_bst;
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bus_space_subregion(tio->tio_bst, tio->tio_bsh,
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loc->loc_offset, loc->loc_size, &sc->sc_bsh);
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KASSERT(pmc_softc == NULL);
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pmc_softc = sc;
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aprint_naive("\n");
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aprint_normal(": CAR\n");
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aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate());
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}
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static void
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tegra_car_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
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{
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if (pmc_softc) {
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*pbst = pmc_softc->sc_bst;
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*pbsh = pmc_softc->sc_bsh;
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} else {
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*pbst = &armv7_generic_bs_tag;
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bus_space_subregion(*pbst, tegra_ppsb_bsh,
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TEGRA_CAR_OFFSET, TEGRA_CAR_SIZE, pbsh);
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}
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}
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u_int
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tegra_car_osc_rate(void)
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{
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return TEGRA_REF_FREQ;
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}
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u_int
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tegra_car_pllx_rate(void)
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{
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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uint64_t rate;
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tegra_car_get_bs(&bst, &bsh);
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rate = tegra_car_osc_rate();
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const uint32_t base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
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const u_int divm = __SHIFTOUT(base, CAR_PLLX_BASE_DIVM);
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const u_int divn = __SHIFTOUT(base, CAR_PLLX_BASE_DIVN);
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const u_int divp = __SHIFTOUT(base, CAR_PLLX_BASE_DIVP);
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rate = tegra_car_osc_rate() * divn;
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return rate / (divm << divp);
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}
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@ -0,0 +1,44 @@
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/* $NetBSD: tegra_carreg.h,v 1.1 2015/04/28 11:15:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_CARREG_H
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#define _ARM_TEGRA_CARREG_H
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#define CAR_PLLX_BASE_REG 0xe0
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#define CAR_PLLX_BASE_ENABLE __BIT(31)
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#define CAR_PLLX_BASE_LOCK_OVERRIDE __BIT(30)
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#define CAR_PLLX_BASE_REF __BIT(29)
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#define CAR_PLLX_BASE_LOCK __BIT(27)
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#define CAR_PLLX_BASE_DIVP __BITS(23,20)
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#define CAR_PLLX_BASE_DIVN __BITS(15,8)
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#define CAR_PLLX_BASE_DIVM __BITS(7,0)
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#define CAR_PLLX_MISC_REG 0xe8
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#endif /* _ARM_TEGRA_CARREG_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_io.c,v 1.2 2015/03/29 22:27:04 jmcneill Exp $ */
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/* $NetBSD: tegra_io.c,v 1.3 2015/04/28 11:15:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "opt_tegra.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.2 2015/03/29 22:27:04 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.3 2015/04/28 11:15:55 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -61,6 +61,11 @@ static bool tegraio_found = false;
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#define NOPORT TEGRAIOCF_PORT_DEFAULT
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#define NOINTR TEGRAIO_INTR_DEFAULT
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static const struct tegra_locators tegra_ppsb_locators[] = {
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{ "tegracar",
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TEGRA_CAR_OFFSET, TEGRA_CAR_SIZE, NOPORT, NOINTR },
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};
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static const struct tegra_locators tegra_apb_locators[] = {
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{ "tegramc",
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TEGRA_MC_OFFSET, TEGRA_MC_SIZE, NOPORT, NOINTR },
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@ -113,6 +118,8 @@ tegraio_attach(device_t parent, device_t self, void *aux)
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aprint_naive("\n");
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aprint_normal(": %s\n", tegra_chip_name());
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tegraio_scan(self, tegra_ppsb_bsh,
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tegra_ppsb_locators, __arraycount(tegra_ppsb_locators));
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tegraio_scan(self, tegra_apb_bsh,
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tegra_apb_locators, __arraycount(tegra_apb_locators));
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tegraio_scan(self, tegra_ahb_a2_bsh,
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_reg.h,v 1.3 2015/04/26 22:04:28 jmcneill Exp $ */
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/* $NetBSD: tegra_reg.h,v 1.4 2015/04/28 11:15:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -87,6 +87,8 @@
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#define TEGRA_XUSB_DEV_SIZE 0xa000
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/* PPSB */
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#define TEGRA_CAR_OFFSET 0x00006000
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#define TEGRA_CAR_SIZE 0x1000
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#define TEGRA_EVP_OFFSET 0x0000f000
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#define TEGRA_EVP_SIZE 0x1000
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/* $NetBSD: tegra_soc.c,v 1.3 2015/04/26 22:04:28 jmcneill Exp $ */
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/* $NetBSD: tegra_soc.c,v 1.4 2015/04/28 11:15:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -30,7 +30,7 @@
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#include "opt_multiprocessor.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.3 2015/04/26 22:04:28 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.4 2015/04/28 11:15:55 jmcneill Exp $");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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@ -81,7 +81,7 @@ tegra_bootstrap(void)
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&tegra_ahb_a2_bsh) != 0)
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panic("couldn't map AHB A2");
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curcpu()->ci_data.cpu_cc_freq = 696000000; /* XXX */
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curcpu()->ci_data.cpu_cc_freq = tegra_car_pllx_rate();
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tegra_mpinit();
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}
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/* $NetBSD: tegra_var.h,v 1.3 2015/04/26 22:04:28 jmcneill Exp $ */
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/* $NetBSD: tegra_var.h,v 1.4 2015/04/28 11:15:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -69,6 +69,9 @@ u_int tegra_chip_id(void);
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const char *tegra_chip_name(void);
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void tegra_bootstrap(void);
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u_int tegra_car_osc_rate(void);
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u_int tegra_car_pllx_rate(void);
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void tegra_pmc_reset(void);
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void tegra_pmc_power(u_int, bool);
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@ -1,5 +1,5 @@
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#
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# $NetBSD: JETSONTK1,v 1.5 2015/04/27 09:56:36 jmcneill Exp $
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# $NetBSD: JETSONTK1,v 1.6 2015/04/28 11:15:55 jmcneill Exp $
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#
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# NVIDIA Jetson TK1 - Tegra K1 development kit
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# https://developer.nvidia.com/jetson-tk1
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@ -41,6 +41,9 @@ tegramc0 at tegraio? # MC
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# Power management controller
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tegrapmc0 at tegraio? # PMC
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# Clock and Reset controller
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tegracar0 at tegraio? # CAR
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# UART
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com3 at tegraio? port 3 # UART-D
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options CONSADDR=0x70006300, CONSPEED=115200
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