gcc.old: vax: PR port-vax/57646 patch provided by Kalvis Duckmanton [21/21]
Define separate instruction patterns for extzv for the cases where the fiel d width and offset happen to be a multiple of a byte or word. If in PIC mode, and the source operand to extzv is a memory reference, and the address of the memory location is an external symbol, load the address into a temporary register before expanding the instruction. Adjust the constraints to the zero_extract instruction pattern to disallow indexed source operands, as the VAX extzv instruction computes offsets based on the size of a byte (not a word or a longword)
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rin
parent
53a1228e9d
commit
8b0d23297f
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@ -827,32 +827,87 @@
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return \"movw %3,%0\";
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}")
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
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;;
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;; Register source, field width is either 8 or 16, field start
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;; is zero - simple, this is a mov[bl].
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;;
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(define_insn "*extzvQISI"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:QI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")))]
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"(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
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&& INTVAL (operands[3]) % INTVAL (operands[2]) == 0
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&& (REG_P (operands[1])
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|| (MEM_P (operands[1])
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&& ! mode_dependent_address_p (XEXP (operands[1], 0),
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MEM_ADDR_SPACE (operands[1]))))"
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"INTVAL (operands[3]) == 0
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&& INTVAL (operands[2]) == GET_MODE_BITSIZE ( QImode )"
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"movzbl %1, %0"
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)
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(define_insn "*extzvHISI"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:QI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")))]
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"INTVAL (operands[3]) == 0
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&& INTVAL (operands[2]) == GET_MODE_BITSIZE ( HImode )"
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"movzwl %1, %0"
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)
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;;
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;; Register source, field width is the entire register
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;;
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(define_insn "*extzvSISI"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:QI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")
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))]
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"INTVAL (operands[3]) == 0
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&& INTVAL (operands[2]) == GET_MODE_BITSIZE ( SImode )"
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"*
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{
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if (REG_P (operands[1]))
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{
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if (INTVAL (operands[3]) != 0)
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return \"extzv %3,%2,%1,%0\";
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}
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else
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operands[1]
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= adjust_address (operands[1],
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INTVAL (operands[2]) == 8 ? QImode : HImode,
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INTVAL (operands[3]) / 8);
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if (rtx_equal_p (operands[0], operands[1]))
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return \"\"; /* no-op */
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return \"movl %1,%0\";
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}")
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if (INTVAL (operands[2]) == 8)
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return \"movzbl %1,%0\";
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;; Register source, non-zero field start is handled elsewhere
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;; Offsettable memory, field width 8 or 16, field start on
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;; boundary matching the field width.
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(define_insn "*extzvQISI2"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:SI 1 "memory_operand" "o")
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(match_operand:QI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")))]
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"INTVAL (operands[2]) == 8
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&& INTVAL (operands[3]) % INTVAL (operands[2]) == 0
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&& ! mode_dependent_address_p (XEXP (operands[1], 0),
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MEM_ADDR_SPACE (operands[1]))"
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"*
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{
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operands[1]
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= adjust_address (operands[1],
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QImode,
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INTVAL (operands[3]) / 8);
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return \"movzbl %1,%0\";
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}")
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(define_insn "*extzvHISI2"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:SI 1 "memory_operand" "o")
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(match_operand:QI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")))]
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"INTVAL (operands[2]) == 16
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&& INTVAL (operands[3]) % INTVAL (operands[2]) == 0
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&& ! mode_dependent_address_p (XEXP (operands[1], 0),
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MEM_ADDR_SPACE (operands[1]))"
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"*
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{
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operands[1]
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= adjust_address (operands[1],
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HImode,
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INTVAL (operands[3]) / 8);
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return \"movzwl %1,%0\";
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}")
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@ -929,17 +984,26 @@
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return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
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}")
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;; When the field position and size are constant and the destination
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;; is a register, extv and extzv are much slower than a rotate followed
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;; by a bicl or sign extension. Because we might end up choosing ext[z]v
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;; anyway, we can't allow immediate values for the primary source operand.
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;; Because some of the instruction sequences generated by this pattern
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;; overwrite the output operand part way through, the output operand
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;; must be marked earlyclobber, may only be a register or memory
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;; operand and must not have any side effects (e.g. pre/post increment)
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;;
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
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(match_operand:QI 2 "general_operand" "g")
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(match_operand:SI 3 "general_operand" "nrmT")))]
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""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=&ro")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:QI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")
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))]
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"INTVAL (operands[3]) != 0"
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"*
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{
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if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
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|| ! REG_P (operands[0]))
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return \"extzv %3,%2,%1,%0\";
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if (INTVAL (operands[2]) == 8)
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return \"rotl %R3,%1,%0\;movzbl %0,%0\";
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if (INTVAL (operands[2]) == 16)
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@ -1041,13 +1105,70 @@
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[(set (match_operand:SI 0 "general_operand" "")
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(zero_extract:SI (match_operand:SI 1 "general_operand" "")
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(match_operand:QI 2 "general_operand" "")
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(match_operand:SI 3 "general_operand" "")))]
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(match_operand:SI 3 "general_operand" ""))
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)]
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""
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"")
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"{
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if (CONST_INT_P (operands[1]))
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{
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/*
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* extzv of a constant doesn't work, so load the constant
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* into a register.
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*/
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rtx temp = gen_reg_rtx (SImode);
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emit_move_insn (temp, operands[1]);
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operands[1] = temp;
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}
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/*
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* If the source operand is a memory reference, and the address
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* is a symbol, and we're in PIC mode, load the address into a
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* register. Don't evaluate the field start or width at this time.
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*/
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if (flag_pic
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/* && !reload_completed */
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&& MEM_P (operands[1])
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&& !mode_dependent_address_p (XEXP (operands[1], 0),
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MEM_ADDR_SPACE (operands[1]))
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&& SYMBOL_REF_P (XEXP (operands[1], 0))
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&& !SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0))
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)
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{
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rtx address = XEXP (operands[1], 0);
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rtx temp = gen_reg_rtx (Pmode);
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emit_move_insn (temp, address);
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/* copy the original memory reference, replacing the address */
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operands[1] = change_address (operands[1], VOIDmode, temp);
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set_mem_align (operands[1], MEM_ALIGN (operands[1]));
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}
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else
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if ((MEM_P (operands[1]) && !CONST_INT_P (operands[2]))
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|| SUBREG_P (operands[1])
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)
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{
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/* Memory addresses for extzv are bytes, so load the source
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operand into a register */
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rtx temp = gen_reg_rtx (SImode);
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emit_move_insn (temp, operands[1]);
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operands[1] = temp;
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}
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else if (address_operand (operands[1], SImode))
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{
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operands[1] = force_reg (SImode, operands[1]);
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}
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}"
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)
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;;
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;; Operand 1 must not, under any circumstances, be an indexed operand
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;; as extzv computes indices based on the size of a byte.
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;;
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=g")
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(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
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[(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
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(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rQ")
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(match_operand:QI 2 "general_operand" "g")
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(match_operand:SI 3 "general_operand" "nrmT")))]
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""
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@ -1056,10 +1177,7 @@
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if (! REG_P (operands[0]) || ! CONST_INT_P (operands[2])
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|| ! CONST_INT_P (operands[3])
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|| INTVAL (operands[2]) + INTVAL (operands[3]) > 32
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|| side_effects_p (operands[1])
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|| (MEM_P (operands[1])
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&& mode_dependent_address_p (XEXP (operands[1], 0),
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MEM_ADDR_SPACE (operands[1]))))
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|| side_effects_p (operands[1]))
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return \"extzv %3,%2,%1,%0\";
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if (INTVAL (operands[2]) == 8)
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return \"rotl %R3,%1,%0\;movzbl %0,%0\";
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