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A small splx()/spl0()/soft interrupt related optimisation. If we're 

dropping to spl0, use inline code to check if a soft interrupt is
pending instead of taking the hit of a function call to do the check.
This commit is contained in:
scw 2000-12-10 18:43:02 +00:00
parent c5b6f43634
commit 8ace7abc75
2 changed files with 45 additions and 27 deletions
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37
sys/arch/mvme68k/include/intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.5 2000/09/19 19:31:34 scw Exp $ */
/* $NetBSD: intr.h,v 1.6 2000/12/10 18:43:02 scw Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -90,11 +90,8 @@
#define splsched() spl7()
#define spllock() spl7()
/* watch out for side effects */
#define splx(s) (s & PSL_IPL ? _spl(s) : spl0())
#ifndef _LOCORE
/*
* Simulated software interrupt register
* This is cleared to zero to indicate a soft interrupt is pending
@ -102,6 +99,35 @@
* instruction so we can avoid masking interrupts elsewhere.)
*/
extern volatile unsigned char ssir;
extern void mvme68k_dossir(void);
static __inline void
splx(int sr)
{
if ((u_int16_t)sr < (u_int16_t)(PSL_IPL1|PSL_S) && ssir == 0)
mvme68k_dossir();
else
__asm __volatile("movw %0,%%sr" : : "di" (sr));
}
static __inline int
spl0(void)
{
int sr;
__asm __volatile("movw %%sr,%0" : "=d" (sr));
if (ssir == 0)
mvme68k_dossir();
else
__asm __volatile("movw %0,%%sr" : : "i" (PSL_LOWIPL));
return sr;
}
#define setsoft(x) x = 0
#define __GENERIC_SOFT_INTERRUPTS
@ -139,7 +165,6 @@ extern struct mvme68k_soft_intrhand *softclock_intrhand;
#define setsoftnet() softintr_schedule(softnet_intrhand)
#define setsoftclock() softintr_schedule(softclock_intrhand)
extern int spl0 __P((void));
#endif /* !_LOCORE */
#endif /* _KERNEL */

35
sys/arch/mvme68k/mvme68k/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.72 2000/11/29 09:11:53 scw Exp $ */
/* $NetBSD: locore.s,v 1.73 2000/12/10 18:43:02 scw Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -1220,6 +1220,19 @@ Lnosir:
Ldorte:
rte | real return
/*
* Set processor priority level calls. Most are implemented with
* inline asm expansions. However, spl0 requires special handling
* as we need to check for our emulated software interrupts.
*/
ENTRY(mvme68k_dossir)
subql #4,%sp | make room for RTE frame
movl %sp@(4),%sp@(2) | position return address
clrw %sp@(6) | set frame type 0
movw #PSL_LOWIPL,%sp@ | and new SR
jra Lgotsir | go handle it
/*
* Use common m68k sigcode.
*/
@ -1611,26 +1624,6 @@ Lploadwskp:
#endif
rts
/*
* Set processor priority level calls. Most are implemented with
* inline asm expansions. However, spl0 requires special handling
* as we need to check for our emulated software interrupts.
*/
ENTRY(spl0)
moveq #0,%d0
movw %sr,%d0 | get old SR for return
movw #PSL_LOWIPL,%sr | restore new SR
tstb _C_LABEL(ssir) | software interrupt pending?
jne Lspldone | no, all done
subql #4,%sp | make room for RTE frame
movl %sp@(4),%sp@(2) | position return address
clrw %sp@(6) | set frame type 0
movw #PSL_LOWIPL,%sp@ | and new SR
jra Lgotsir | go handle it
Lspldone:
rts
ENTRY(getsr)
moveq #0,%d0
movw %sr,%d0