parent
4b5976925c
commit
89d25dc1ce
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@ -371,7 +371,8 @@
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#define AWIN_EMAC_SAFX3_L_REG 0x00BC
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#define AWIN_EMAC_SAFX3_H_REG 0x00C0
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#define AWIN_ACHI_BISTAFR_REG 0x00A0
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#define AWIN_AHCI_DMA_REG 0x0070
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#define AWIN_AHCI_BISTAFR_REG 0x00A0
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#define AWIN_AHCI_BISTCR_REG 0x00A4
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#define AWIN_AHCI_BISTFCTR_REG 0x00A8
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#define AWIN_AHCI_BISTSR_REG 0x00AC
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@ -471,17 +472,22 @@
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#define AWIN_PLL_CFG_ENABLE __BIT(31)
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#define AWIN_PLL_CFG_BYPASS __BIT(30)
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#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
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#define AWIN_PLL_CFG_EXG_MODE __BIT(25)
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#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16)
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#define AWIN_PLL6_CFG_SATA_CLK_EN __BIT(14)
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#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8)
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#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
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#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4)
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#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
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#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
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#define AWIN_PLL1_SIG_DELT_PAT_IN __BIT(3)
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#define AWIN_PLL1_SIG_DELT_PAT_EN __BIT(2)
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#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
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#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
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#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
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#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
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#define AWIN_PLL6_VCO_BIAS __BITS(29,25)
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#define AWIN_PLL6_PLL_BIAS __BITS(24,20)
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#define AWIN_PLL6_CFG_SATA_CLK_EN __BIT(14)
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#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16)
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#define AWIN_CPU_CLK_SRC_SEL_LOSC 0
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