now in sys/dev
This commit is contained in:
gwr
parent
9e07977e11
commit
89c2f6dc04
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MI 5380 driver
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==============
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(What? Documentation? Is this guy nuts? :-)
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Reselection
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-----------
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This driver will permit reselection on non-polled commands if
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sc->sc_flags & NCR5380_PERMIT_RESELECT is 1. This permits enabling of
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reselection on a per-device basis.
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Disconnect/reselect is never permitted for polled commands.
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Interfacing the driver to MD code
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---------------------------------
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/sys/dev/ic/ncr5380.c is now stand-alone. DON'T include it after your
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MD stuff!
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This allows for more than one 5380-based SCSI board in your system. This is
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a real possibility for Amiga generic kernels.
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Your driver's softc structure must have an instance of struct ncr5380_softc
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as the first thing in the structure. The MD code must initialize the
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following:
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sci_*: pointers to the 5380 registers. All accesses are done through
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these pointers. This indirection allows the driver to work with
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boards that map the 5380 on even addresses only or do other
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wierdnesses.
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int (*sc_pio_out)(sc, phase, datalen, data)
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int (*sc_pio_in)(sc, phase, datalen, data)
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These point to functions that do programmed I/O transfers to the bus and
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from the bus, respectively. Arguments:
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sc points to the softc
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phase the current SCSI bus phase
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datalen length of data to transfer
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data pointer to the buffer
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Both functions must return the number of bytes successfully transferred.
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A transfer operation must be aborted if the target requests a different
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phase before the transfer completes.
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If you have no special requirements, you can point these to
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ncr5380_pio_out() and ncr5380_pio_in() respectively. If your board
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can do pseudo-DMA, then you might want to point these to functions
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that use this feature.
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void (*sc_dma_alloc)(sc)
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This function is called to set up a DMA transfer. You must create and
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return a "DMA handle" in sc->sc_dma_hand which identifies the DMA transfer.
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The driver will pass you your DMA handle in sc->sc_dma_hand for future
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operations. The contents of the DMA handle are immaterial to the MI
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code - the DMA handle is for your bookkeeping only. Usually, you
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create a structure and point to it here.
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For example, you can record the mapped and unmapped addresses of the
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buffer. The Sun driver places an Am9516 UDC control block in the DMA
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handle.
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If for some reason you decide not to do DMA for the transfer, make
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sc->sc_dma_hand NULL. This might happen if the proposed transfer is
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misaligned, or in the wrong type of memory, or...
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void (*sc_dma_start)(sc)
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This function starts the transfer.
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void (*sc_dma_stop)(sc)
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This function stops a transfer. sc->sc_datalen and sc->sc_dataptr must
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be updated to reflect the portion of the DMA already done.
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void (*sc_dma_eop)(sc)
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This function is called when the 5380 signals EOP. Either continue
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the DMA or stop the DMA.
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void (*sc_dma_free)(sc)
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This function frees the current DMA handle.
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u_char *sc_dataptr;
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int sc_datalen;
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These variables form the active SCSI data pointer. DMA code must start
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DMA at the location given, and update the pointer/length in response to
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DMA operations.
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u_short sc_dma_flags;
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See ncr5380var.h
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Writing your DMA code
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---------------------
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DMA on a system with protected or virtual memory is always a problem. Even
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though a disk transfer may be logically contiguous, the physical pages backing
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the transfer may not be. There are two common solutions to this problem:
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DMA chains: the DMA is broken up into a list of contiguous segments. The first
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segment is submitted to the DMA controller, and when it completes, the second
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segment is submitted, without stopping the 5380. This is what the sc_dma_eop()
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function can do efficiently - if you have a DMA chain, it can quickly load up
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the next link in the chain. The sc_dma_alloc() function builds the chain and
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sc_dma_free() releases any resources you used to build it.
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DVMA: Direct Virtual Memory Access. In this scheme, DMA requests go through
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the MMU. Although you can't page fault, you can program the MMU to remap
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things so the DMA controller sees contiguous data. In this mode, sc_dma_alloc()
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is used to map the transfer into the address space reserved for DVMA and
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sc_dma_free() is used to unmap it.
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Interrupts
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----------
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ncr5380_sbc_intr() must be called when the 5380 interrupts the host.
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You must write an interrupt routine pretty much from scratch to check for
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things generated by MD hardware.
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Known problems
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--------------
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I'm getting this out now so that other ports can hack on it and integrate it.
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The sun3, DMA/Interrupt appears to be working now, but needs testing.
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Polled commands submitted while non-polled commands are in progress are not
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handled correctly. This can happen if reselection is enabled and a new disk
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is mounted while an I/O is in progress on another disk.
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The problem is: what to do if you get reselected while doing the selection
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for the polled command? Currently, the driver busy waits for the non-polled
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command to complete, but this is bogus. I need to complete the non-polled
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command in polled mode, then do the polled command.
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Timeouts in the driver are EXTREMELY sensitive to the characteristics of the
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local implementation of delay(). The Sun3 version delays for a minimum of 5us.
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However, the driver must assume that delay(1) will delay only 1us. For this
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reason, performance on the Sun3 sucks in some places.
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@ -1,160 +0,0 @@
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/* $NetBSD: ncr5380reg.h,v 1.2 1995/11/17 23:27:41 gwr Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* HISTORY (mach3)
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* Revision 2.3 91/08/24 12:25:10 af
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* Moved padding of regmap in impl file.
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* [91/08/02 04:22:39 af]
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*
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* Revision 2.2 91/06/19 16:28:35 rvb
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* From the NCR data sheets
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* "NCR 5380 Family, SCSI Protocol Controller Data Manual"
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* NCR Microelectronics Division, Colorado Spring, 6/98 T01891L
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* [91/04/21 af]
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*
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*/
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/*
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* File: scsi_5380.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 5/91
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*
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* Defines for the NCR 5380 (SCSI chip), aka Am5380
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*/
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/*
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* Register map: Note not declared here anymore!
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* All the 5380 registers are accessed through individual
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* pointers initialized by MD code. This allows the 5380
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* MI functions to be shared between MD drivers that have
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* different padding between the registers (i.e. amiga).
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*/
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#if 0 /* example only */
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struct ncr5380regs {
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volatile u_char sci_r0;
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volatile u_char sci_r1;
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volatile u_char sci_r2;
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volatile u_char sci_r3;
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volatile u_char sci_r4;
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volatile u_char sci_r5;
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volatile u_char sci_r6;
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volatile u_char sci_r7;
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};
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#endif
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/*
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* Machine-independent code uses these names:
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*/
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#define sci_data sci_r0 /* r: Current data */
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#define sci_odata sci_r0 /* w: Out data */
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#define sci_icmd sci_r1 /* rw: Initiator command */
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#define sci_mode sci_r2 /* rw: Mode */
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#define sci_tcmd sci_r3 /* rw: Target command */
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#define sci_bus_csr sci_r4 /* r: Bus Status */
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#define sci_sel_enb sci_r4 /* w: Select enable */
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#define sci_csr sci_r5 /* r: Status */
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#define sci_dma_send sci_r5 /* w: Start dma send data */
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#define sci_idata sci_r6 /* r: Input data */
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#define sci_trecv sci_r6 /* w: Start dma receive, target */
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#define sci_iack sci_r7 /* r: Interrupt Acknowledge */
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#define sci_irecv sci_r7 /* w: Start dma receive, initiator */
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/*
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* R1: Initiator command register
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*/
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#define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
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#define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
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#define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
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#define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
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#define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
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#define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
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#define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
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#define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
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#define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
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#define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
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/* Bits to keep when doing read/modify/write (leave out RST) */
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#define SCI_ICMD_RMASK 0x1F
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/*
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* R2: Mode register
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*/
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#define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
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#define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
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#define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
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#define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
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#define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
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#define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
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#define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
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#define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake */
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/*
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* R3: Target command register
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*/
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#define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
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#define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
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#define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
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#define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
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#define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
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#define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
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* (not on 5380/1) */
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#define SCI_TCMD_PHASE(x) ((x) & 0x7)
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/*
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* R4: Current (SCSI) Bus status (.sci_bus_csr)
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*/
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#define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
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#define SCI_BUS_SEL 0x02 /* r: SEL signal */
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#define SCI_BUS_IO 0x04 /* r: I/O signal */
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#define SCI_BUS_CD 0x08 /* r: C/D signal */
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#define SCI_BUS_MSG 0x10 /* r: MSG signal */
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#define SCI_BUS_REQ 0x20 /* r: REQ signal */
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#define SCI_BUS_BSY 0x40 /* r: BSY signal */
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#define SCI_BUS_RST 0x80 /* r: RST signal */
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#define SCI_BUS_PHASE(x) (((x) >> 2) & 7)
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/*
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* R5: Bus and Status register (.sci_csr)
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*/
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#define SCI_CSR_ACK 0x01 /* r: ACK signal */
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#define SCI_CSR_ATN 0x02 /* r: ATN signal */
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#define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
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#define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
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#define SCI_CSR_INT 0x10 /* r: Interrupt request */
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#define SCI_CSR_PERR 0x20 /* r: Parity error */
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#define SCI_CSR_DREQ 0x40 /* r: DMA request */
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#define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
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File diff suppressed because it is too large
Load Diff
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@ -1,178 +0,0 @@
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/* $NetBSD: ncr5380var.h,v 1.2 1995/11/17 23:27:49 gwr Exp $ */
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/*
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* Copyright (c) 1995 David Jones, Gordon W. Ross
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* Copyright (c) 1994 Jarle Greipsland
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* David Jones and Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file defines the interface between the machine-dependent
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* module and the machine-indepenedent ncr5380sbc.c module.
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*/
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#define SCI_CLR_INTR(sc) (*(sc)->sci_iack)
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#define SCI_BUSY(sc) (*sc->sci_bus_csr & SCI_BUS_BSY)
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/* These are NOT artibtrary, but map to bits in sci_tcmd */
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#define PHASE_DATA_OUT 0x0
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#define PHASE_DATA_IN 0x1
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#define PHASE_COMMAND 0x2
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#define PHASE_STATUS 0x3
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#define PHASE_UNSPEC1 0x4
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#define PHASE_UNSPEC2 0x5
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#define PHASE_MSG_OUT 0x6
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#define PHASE_MSG_IN 0x7
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||||||
|
|
||||||
/*
|
|
||||||
* This illegal phase is used to prevent the 5380 from having
|
|
||||||
* a phase-match condition when we don't want one, such as
|
|
||||||
* when setting up the DMA engine or whatever...
|
|
||||||
*/
|
|
||||||
#define PHASE_INVALID PHASE_UNSPEC1
|
|
||||||
|
|
||||||
|
|
||||||
/* Per-request state. This is required in order to support reselection. */
|
|
||||||
struct sci_req {
|
|
||||||
struct scsi_xfer *sr_xs; /* Pointer to xfer struct, NULL=unused */
|
|
||||||
int sr_target, sr_lun; /* For fast access */
|
|
||||||
void *sr_dma_hand; /* Current DMA hnadle */
|
|
||||||
u_char *sr_dataptr; /* Saved data pointer */
|
|
||||||
int sr_datalen;
|
|
||||||
int sr_flags; /* Internal error code */
|
|
||||||
#define SR_IMMED 1 /* Immediate command */
|
|
||||||
#define SR_SENSE 2 /* We are getting sense */
|
|
||||||
#define SR_OVERDUE 4 /* Timeout while not current */
|
|
||||||
#define SR_ERROR 8 /* Error occurred */
|
|
||||||
int sr_status; /* Status code from last cmd */
|
|
||||||
};
|
|
||||||
#define SCI_OPENINGS 16 /* How many commands we can enqueue. */
|
|
||||||
|
|
||||||
|
|
||||||
struct ncr5380_softc {
|
|
||||||
struct device sc_dev;
|
|
||||||
struct scsi_link sc_link;
|
|
||||||
|
|
||||||
/* Pointers to 5380 registers. See ncr5380reg.h */
|
|
||||||
volatile u_char *sci_r0;
|
|
||||||
volatile u_char *sci_r1;
|
|
||||||
volatile u_char *sci_r2;
|
|
||||||
volatile u_char *sci_r3;
|
|
||||||
volatile u_char *sci_r4;
|
|
||||||
volatile u_char *sci_r5;
|
|
||||||
volatile u_char *sci_r6;
|
|
||||||
volatile u_char *sci_r7;
|
|
||||||
|
|
||||||
/* Functions set from MD code */
|
|
||||||
int (*sc_pio_out) __P((struct ncr5380_softc *,
|
|
||||||
int, int, u_char *));
|
|
||||||
int (*sc_pio_in) __P((struct ncr5380_softc *,
|
|
||||||
int, int, u_char *));
|
|
||||||
void (*sc_dma_alloc) __P((struct ncr5380_softc *));
|
|
||||||
void (*sc_dma_free) __P((struct ncr5380_softc *));
|
|
||||||
|
|
||||||
void (*sc_dma_setup) __P((struct ncr5380_softc *));
|
|
||||||
void (*sc_dma_start) __P((struct ncr5380_softc *));
|
|
||||||
void (*sc_dma_poll) __P((struct ncr5380_softc *));
|
|
||||||
void (*sc_dma_eop) __P((struct ncr5380_softc *));
|
|
||||||
void (*sc_dma_stop) __P((struct ncr5380_softc *));
|
|
||||||
|
|
||||||
void (*sc_intr_on) __P((struct ncr5380_softc *));
|
|
||||||
void (*sc_intr_off) __P((struct ncr5380_softc *));
|
|
||||||
|
|
||||||
int sc_flags; /* Misc. flags and capabilities */
|
|
||||||
#define NCR5380_PERMIT_RESELECT 1 /* Allow disconnect/reselect */
|
|
||||||
#define NCR5380_FORCE_POLLING 2 /* Do not use interrupts. */
|
|
||||||
|
|
||||||
int sc_min_dma_len; /* Smaller than this is done with PIO */
|
|
||||||
|
|
||||||
/* Begin MI shared data */
|
|
||||||
|
|
||||||
int sc_state;
|
|
||||||
#define NCR_IDLE 0 /* Ready for new work. */
|
|
||||||
#define NCR_WORKING 0x01 /* Some command is in progress. */
|
|
||||||
#define NCR_ABORTING 0x02 /* Bailing out */
|
|
||||||
#define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
|
|
||||||
#define NCR_DROP_MSGIN 0x10 /* Discard all msgs (parity err detected) */
|
|
||||||
|
|
||||||
/* The request that has the bus now. */
|
|
||||||
struct sci_req *sc_current;
|
|
||||||
|
|
||||||
/* Active data pointer for current SCSI command. */
|
|
||||||
u_char *sc_dataptr;
|
|
||||||
int sc_datalen;
|
|
||||||
|
|
||||||
/* Begin MI private data */
|
|
||||||
|
|
||||||
/* The number of operations in progress on the bus */
|
|
||||||
volatile int sc_ncmds;
|
|
||||||
|
|
||||||
/* Ring buffer of pending/active requests */
|
|
||||||
struct sci_req sc_ring[SCI_OPENINGS];
|
|
||||||
int sc_rr; /* Round-robin scan pointer */
|
|
||||||
|
|
||||||
/* Active requests, by target/LUN */
|
|
||||||
struct sci_req *sc_matrix[8][8];
|
|
||||||
|
|
||||||
/* Message stuff */
|
|
||||||
int sc_prevphase;
|
|
||||||
|
|
||||||
u_int sc_msgpriq; /* Messages we want to send */
|
|
||||||
u_int sc_msgoutq; /* Messages sent during last MESSAGE OUT */
|
|
||||||
u_int sc_msgout; /* Message last transmitted */
|
|
||||||
#define SEND_DEV_RESET 0x01
|
|
||||||
#define SEND_PARITY_ERROR 0x02
|
|
||||||
#define SEND_ABORT 0x04
|
|
||||||
#define SEND_REJECT 0x08
|
|
||||||
#define SEND_INIT_DET_ERR 0x10
|
|
||||||
#define SEND_IDENTIFY 0x20
|
|
||||||
#define SEND_SDTR 0x40
|
|
||||||
#define SEND_WDTR 0x80
|
|
||||||
#define NCR_MAX_MSG_LEN 8
|
|
||||||
u_char sc_omess[NCR_MAX_MSG_LEN];
|
|
||||||
u_char *sc_omp; /* Outgoing message pointer */
|
|
||||||
u_char sc_imess[NCR_MAX_MSG_LEN];
|
|
||||||
u_char *sc_imp; /* Incoming message pointer */
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
void ncr5380_init __P((struct ncr5380_softc *));
|
|
||||||
void ncr5380_reset_scsibus __P((struct ncr5380_softc *));
|
|
||||||
int ncr5380_intr __P((struct ncr5380_softc *));
|
|
||||||
int ncr5380_scsi_cmd __P((struct scsi_xfer *));
|
|
||||||
int ncr5380_pio_in __P((struct ncr5380_softc *, int, int, u_char *));
|
|
||||||
int ncr5380_pio_out __P((struct ncr5380_softc *, int, int, u_char *));
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
struct ncr5380_softc *ncr5380_debug_sc;
|
|
||||||
void ncr5380_trace __P((char *msg, long val));
|
|
||||||
#define NCR_TRACE(msg, val) ncr5380_trace(msg, val)
|
|
||||||
#else
|
|
||||||
#define NCR_TRACE(msg, val) /* nada */
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in New Issue