Improve SB800 and newer chipsets support:
- Add newer chipset (e.g. X370/X399 and newer) support that the PCI device id is 0x790b. The register definitions are mainly taken from FreeBSD. - Rename PIIXPM_INDIRECTIO_* to SB800_INDIRECTIO_* because those are only for SB800 and newer chipsets. - SB800 also support 4 ports. - SB800's interrupt configuration bit is different from others. Use SB800_SMB_HOSTC's bit 0. - Do not bus_space_map devices which are at address 0 (it's uninitialized) in piixpm_attach(). - Add the port number to the dmesg output. - Avoid uninitiliazed use of ctl and corresponding warnings. From OpenBSD rev. 1.38
This commit is contained in:
msaitoh
parent
a713a1068c
commit
88e2c8620e
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@ -1,5 +1,5 @@
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/* $NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $ */
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/* $OpenBSD: piixpm.c,v 1.35 2011/04/09 04:33:40 deraadt Exp $ */
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/* $NetBSD: piixpm.c,v 1.54 2019/07/13 09:24:17 msaitoh Exp $ */
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/* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */
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/*
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* Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org>
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@ -22,7 +22,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.54 2019/07/13 09:24:17 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -49,12 +49,27 @@ __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $");
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#define DPRINTF(x)
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#endif
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#define PIIXPM_IS_CSB5(id) \
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(PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \
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PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5)
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#define PIIXPM_IS_CSB5(sc) \
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(PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \
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PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5)
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#define PIIXPM_DELAY 200
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#define PIIXPM_TIMEOUT 1
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#define PIIXPM_IS_SB800GRP(sc) \
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((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \
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((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \
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((sc)->sc_rev >= 0x40)))
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#define PIIXPM_IS_HUDSON(sc) \
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((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \
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(PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB))
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#define PIIXPM_IS_KERNCZ(sc) \
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((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \
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(PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB))
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#define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc))
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struct piixpm_smbus {
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int sda;
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struct piixpm_softc *softc;
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@ -75,6 +90,7 @@ struct piixpm_softc {
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pcitag;
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pcireg_t sc_id;
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pcireg_t sc_rev;
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int sc_numbusses;
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device_t sc_i2c_device[4];
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@ -149,6 +165,7 @@ piixpm_match(device_t parent, cfdata_t match, void *aux)
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case PCI_VENDOR_AMD:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_AMD_HUDSON_SMB:
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case PCI_PRODUCT_AMD_KERNCZ_SMB:
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return 1;
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}
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break;
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@ -165,6 +182,7 @@ piixpm_attach(device_t parent, device_t self, void *aux)
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pcireg_t base, conf;
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pcireg_t pmmisc;
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pci_intr_handle_t ih;
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bool usesmi = false;
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const char *intrstr = NULL;
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int i, flags;
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char intrbuf[PCI_INTRSTR_LEN];
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@ -172,6 +190,7 @@ piixpm_attach(device_t parent, device_t self, void *aux)
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sc->sc_dev = self;
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sc->sc_iot = pa->pa_iot;
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sc->sc_id = pa->pa_id;
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sc->sc_rev = PCI_REVISION(pa->pa_class);
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sc->sc_pc = pa->pa_pc;
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sc->sc_pcitag = pa->pa_tag;
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sc->sc_numbusses = 1;
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@ -181,10 +200,6 @@ piixpm_attach(device_t parent, device_t self, void *aux)
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if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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/* Read configuration */
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conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
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DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf));
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if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
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(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
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goto nopowermanagement;
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@ -208,48 +223,52 @@ piixpm_attach(device_t parent, device_t self, void *aux)
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* PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
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* in the "Specification update" (document #297738).
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*/
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acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh,
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PIIX_PM_PMTMR,
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(PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 );
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acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR,
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(PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0);
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nopowermanagement:
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/* SB800 rev 0x40+ and AMD HUDSON need special initialization */
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) {
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if (piixpm_sb800_init(sc) == 0) {
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goto attach_i2c;
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}
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aprint_normal_dev(self, "SMBus initialization failed\n");
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return;
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}
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB &&
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PCI_REVISION(pa->pa_class) >= 0x40) {
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/* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */
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if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) {
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if (piixpm_sb800_init(sc) == 0) {
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sc->sc_numbusses = 4;
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goto attach_i2c;
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/* Read configuration */
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conf = pci_conf_read(pa->pa_pc, pa->pa_tag,
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SB800_SMB_HOSTC);
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DPRINTF(("%s: conf 0x%08x\n", device_xname(self),
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conf));
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usesmi = conf & SB800_SMB_HOSTC_SMI;
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goto setintr;
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}
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aprint_normal_dev(self, "SMBus initialization failed\n");
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return;
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}
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/* Read configuration */
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conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
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DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf));
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if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
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aprint_normal_dev(self, "SMBus disabled\n");
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return;
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}
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usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI;
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/* Map I/O space */
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base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
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if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
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if (base == 0 ||
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bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
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PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
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aprint_error_dev(self, "can't map smbus I/O space\n");
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return;
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}
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setintr:
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sc->sc_poll = 1;
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aprint_normal_dev(self, "");
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if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
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if (usesmi) {
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/* No PCI IRQ */
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aprint_normal("interrupting at SMI, ");
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} else {
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@ -274,7 +293,6 @@ nopowermanagement:
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aprint_normal("\n");
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attach_i2c:
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for (i = 0; i < sc->sc_numbusses; i++)
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sc->sc_i2c_device[i] = NULL;
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@ -283,6 +301,20 @@ attach_i2c:
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piixpm_rescan(self, "i2cbus", &flags);
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}
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static int
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piixpm_iicbus_print(void *aux, const char *pnp)
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{
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struct i2cbus_attach_args *iba = aux;
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struct i2c_controller *tag = iba->iba_tag;
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struct piixpm_smbus *bus = tag->ic_cookie;
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struct piixpm_softc *sc = bus->softc;
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iicbus_print(aux, pnp);
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if (sc->sc_numbusses != 0)
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aprint_normal(" port %d", bus->sda);
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return UNCONF;
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}
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static int
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piixpm_rescan(device_t self, const char *ifattr, const int *flags)
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{
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@ -308,7 +340,7 @@ piixpm_rescan(device_t self, const char *ifattr, const int *flags)
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iba.iba_type = I2C_TYPE_SMBUS;
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iba.iba_tag = &sc->sc_i2c_tags[i];
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sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba,
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iicbus_print);
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piixpm_iicbus_print);
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}
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return 0;
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@ -367,39 +399,53 @@ piixpm_sb800_init(struct piixpm_softc *sc)
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh; /* indirect I/O handle */
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uint16_t val, base_addr;
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bool enabled;
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/* Fetch SMB base address */
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if (bus_space_map(iot,
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PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) {
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SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) {
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device_printf(sc->sc_dev, "couldn't map indirect I/O space\n");
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return EBUSY;
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}
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bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
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SB800_PM_SMBUS0EN_LO);
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val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA);
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bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
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SB800_PM_SMBUS0EN_HI);
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val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8;
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if (PIIXPM_IS_FCHGRP(sc)) {
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bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
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AMDFCH41_PM_DECODE_EN0);
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val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
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enabled = val & AMDFCH41_SMBUS_EN;
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if (!enabled)
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return ENOENT;
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bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
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AMDFCH41_PM_DECODE_EN1);
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val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8;
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base_addr = val;
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} else {
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bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
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SB800_PM_SMBUS0EN_LO);
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val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
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enabled = val & SB800_PM_SMBUS0EN_ENABLE;
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if (!enabled)
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return ENOENT;
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bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
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SB800_PM_SMBUS0EN_HI);
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val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8;
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base_addr = val & SB800_PM_SMBUS0EN_BADDR;
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bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
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SB800_PM_SMBUS0SELEN);
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bus_space_write_1(iot, ioh, SB800_INDIRECTIO_DATA,
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SB800_PM_SMBUS0EN_ENABLE);
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}
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sc->sc_sb800_ioh = ioh;
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if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0)
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return ENOENT;
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base_addr = val & SB800_PM_SMBUS0EN_BADDR;
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aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr);
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bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
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SB800_PM_SMBUS0SELEN);
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bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */
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if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr),
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PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
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aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n");
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return EBUSY;
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}
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aprint_normal_dev(sc->sc_dev, "polling (SB800)\n");
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sc->sc_poll = 1;
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return 0;
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}
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@ -434,12 +480,16 @@ piixpm_i2c_acquire_bus(void *cookie, int flags)
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if (!cold)
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mutex_enter(&sc->sc_i2c_mutex);
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if (smbus->sda > 0) /* SB800 */
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{
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if (PIIXPM_IS_KERNCZ(sc)) {
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
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SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX);
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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PIIXPM_INDIRECTIO_DATA, smbus->sda << 1);
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SB800_INDIRECTIO_DATA, smbus->sda << 3);
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} else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) {
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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SB800_INDIRECTIO_DATA, smbus->sda << 1);
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}
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return 0;
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@ -451,16 +501,20 @@ piixpm_i2c_release_bus(void *cookie, int flags)
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struct piixpm_smbus *smbus = cookie;
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struct piixpm_softc *sc = smbus->softc;
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if (smbus->sda > 0) /* SB800 */
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{
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if (PIIXPM_IS_KERNCZ(sc)) {
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX);
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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SB800_INDIRECTIO_DATA, 0);
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} else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) {
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/*
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* HP Microserver hangs after reboot if not set to SDA0.
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* Also add shutdown hook?
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*/
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
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SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
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bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
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PIIXPM_INDIRECTIO_DATA, 0);
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SB800_INDIRECTIO_DATA, 0);
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}
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if (!cold)
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@ -473,8 +527,8 @@ piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
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{
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struct piixpm_smbus *smbus = cookie;
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struct piixpm_softc *sc = smbus->softc;
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const u_int8_t *b;
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u_int8_t ctl = 0, st;
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const uint8_t *b;
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uint8_t ctl = 0, st;
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int retries;
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DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, "
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@ -549,6 +603,8 @@ piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
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ctl = PIIX_SMB_HC_CMD_BDATA;
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else if (len == 2)
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ctl = PIIX_SMB_HC_CMD_WDATA;
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else
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panic("%s: unexpected len %zu", __func__, len);
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if ((flags & I2C_F_POLL) == 0)
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ctl |= PIIX_SMB_HC_INTREN;
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@ -559,7 +615,7 @@ piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
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if (flags & I2C_F_POLL) {
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/* Poll for completion */
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if (PIIXPM_IS_CSB5(sc->sc_id))
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if (PIIXPM_IS_CSB5(sc))
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DELAY(2*PIIXPM_DELAY);
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else
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DELAY(PIIXPM_DELAY);
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@ -600,7 +656,7 @@ timeout:
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/*
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* CSB5 needs hard reset to unlock the smbus after timeout.
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*/
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if (PIIXPM_IS_CSB5(sc->sc_id))
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if (PIIXPM_IS_CSB5(sc))
|
||||
piixpm_csb5_reset(sc);
|
||||
return (1);
|
||||
}
|
||||
|
|
@ -609,8 +665,8 @@ static int
|
|||
piixpm_intr(void *arg)
|
||||
{
|
||||
struct piixpm_softc *sc = arg;
|
||||
u_int8_t st;
|
||||
u_int8_t *b;
|
||||
uint8_t st;
|
||||
uint8_t *b;
|
||||
size_t len;
|
||||
|
||||
/* Read status */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,34 @@
|
|||
/* $NetBSD: piixpmreg.h,v 1.7 2014/03/18 18:20:42 riastradh Exp $ */
|
||||
/* $NetBSD: piixpmreg.h,v 1.8 2019/07/13 09:24:17 msaitoh Exp $ */
|
||||
/* $OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD: head/sys/dev/amdsbwd/amd_chipset.h 333269 2018-05-05 05:22:11Z avg $
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
|
||||
*
|
||||
|
|
@ -75,10 +103,16 @@
|
|||
#define PIIX_PM_SIZE 0x38 /* Power management I/O space size */
|
||||
#define PIIX_SMB_SIZE 0x10 /* SMBus I/O space size */
|
||||
|
||||
#define PIIXPM_INDIRECTIO_BASE 0xcd6
|
||||
#define PIIXPM_INDIRECTIO_SIZE 2
|
||||
#define PIIXPM_INDIRECTIO_INDEX 0
|
||||
#define PIIXPM_INDIRECTIO_DATA 1
|
||||
/*
|
||||
* AMD SB800 and compatible chipset's configuration registers.
|
||||
* See SB8xx RRG 2.3.3, etc.
|
||||
*/
|
||||
|
||||
/* In the I/O area */
|
||||
#define SB800_INDIRECTIO_BASE 0xcd6
|
||||
#define SB800_INDIRECTIO_SIZE 2
|
||||
#define SB800_INDIRECTIO_INDEX 0
|
||||
#define SB800_INDIRECTIO_DATA 1
|
||||
|
||||
#define SB800_PM_SMBUS0EN_LO 0x2c
|
||||
#define SB800_PM_SMBUS0EN_HI 0x2d
|
||||
|
|
@ -88,4 +122,28 @@
|
|||
#define SB800_PM_SMBUS0EN_ENABLE 0x0001
|
||||
#define SB800_PM_SMBUS0EN_BADDR 0xffe0
|
||||
|
||||
/* In the PCI config space */
|
||||
#define SB800_SMB_HOSTC 0x10 /* I2C bus configuration */
|
||||
#define SB800_SMB_HOSTC_SMI (1 << 0) /* SMI */
|
||||
|
||||
/*
|
||||
* Newer FCH registers in the PMIO space.
|
||||
* See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04.
|
||||
*/
|
||||
#define AMDFCH41_PM_DECODE_EN0 0x00
|
||||
#define AMDFCH41_SMBUS_EN 0x10
|
||||
#define AMDFCH41_WDT_EN 0x80
|
||||
#define AMDFCH41_PM_DECODE_EN1 0x01
|
||||
#define AMDFCH41_PM_PORT_INDEX 0x02
|
||||
#define AMDFCH41_PM_DECODE_EN3 0x03
|
||||
#define AMDFCH41_WDT_RES_MASK 0x03
|
||||
#define AMDFCH41_WDT_RES_32US 0x00
|
||||
#define AMDFCH41_WDT_RES_10MS 0x01
|
||||
#define AMDFCH41_WDT_RES_100MS 0x02
|
||||
#define AMDFCH41_WDT_RES_1S 0x03
|
||||
#define AMDFCH41_WDT_EN_MASK 0x0c
|
||||
#define AMDFCH41_WDT_ENABLE 0x00
|
||||
#define AMDFCH41_PM_ISA_CTRL 0x04
|
||||
#define AMDFCH41_MMIO_EN 0x02
|
||||
|
||||
#endif /* !_DEV_PCI_PIIXREG_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue