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Convert to aprint_*

This commit is contained in:
uwe 2007-11-06 01:33:00 +00:00
parent 8b4bf162e5
commit 88c74cddaf
3 changed files with 39 additions and 34 deletions
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48
sys/arch/sh3/sh3/cache.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.c,v 1.12 2006/09/24 00:43:44 tsutsui Exp $ */
/* $NetBSD: cache.c,v 1.13 2007/11/06 01:33:00 uwe Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.12 2006/09/24 00:43:44 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.13 2007/11/06 01:33:00 uwe Exp $");
#include "opt_memsize.h" /* IOM_RAM_BEGIN */
@ -107,45 +107,47 @@ sh_cache_information()
#endif
/* I-cache or I/D-unified cache */
printf("cpu0: %dKB/%dB",
sh_cache_size_icache >> 10, sh_cache_line_size);
aprint_normal("cpu0: %dKB/%dB",
sh_cache_size_icache >> 10,
sh_cache_line_size);
if (sh_cache_ways > 1)
printf(" %d-way set-associative", sh_cache_ways);
aprint_normal(" %d-way set-associative", sh_cache_ways);
else
printf(" direct-mapped");
aprint_normal(" direct-mapped");
if (sh_cache_unified)
printf(" I/D-unified");
aprint_normal(" I/D-unified cache.");
else
printf(" Instruction");
printf(" cache.");
aprint_normal(" Instruction cache.");
if (!sh_cache_enable_icache)
printf(" DISABLED");
aprint_normal(" DISABLED");
if (sh_cache_unified && sh_cache_ram_mode)
printf(" RAM-mode");
aprint_normal(" RAM-mode");
if (sh_cache_index_mode_icache)
printf(" INDEX-mode");
printf("\n");
aprint_normal(" INDEX-mode");
aprint_normal("\n");
/* D-cache */
if (!sh_cache_unified) {
printf("cpu0: %dKB/%dB", sh_cache_size_dcache >> 10,
sh_cache_line_size);
aprint_normal("cpu0: %dKB/%dB",
sh_cache_size_dcache >> 10,
sh_cache_line_size);
if (sh_cache_ways > 1)
printf(" %d-way set-associative", sh_cache_ways);
aprint_normal(" %d-way set-associative",
sh_cache_ways);
else
printf(" direct-mapped");
printf(" Data cache.");
aprint_normal(" direct-mapped");
aprint_normal(" Data cache.");
if (!sh_cache_enable_dcache)
printf(" DISABLED");
aprint_normal(" DISABLED");
if (sh_cache_ram_mode)
printf(" RAM-mode");
aprint_normal(" RAM-mode");
if (sh_cache_index_mode_dcache)
printf(" INDEX-mode");
printf("\n");
aprint_normal(" INDEX-mode");
aprint_normal("\n");
}
/* Write-through/back */
printf("cpu0: P0, U0, P3 write-%s; P1 write-%s\n",
aprint_normal("cpu0: P0, U0, P3 write-%s; P1 write-%s\n",
sh_cache_write_through_p0_u0_p3 ? "through" : "back",
sh_cache_write_through_p1 ? "through" : "back");
}

7
sys/arch/sh3/sh3/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.9 2006/10/11 01:08:48 uwe Exp $ */
/* $NetBSD: cpu.c,v 1.10 2007/11/06 01:33:00 uwe Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.9 2006/10/11 01:08:48 uwe Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.10 2007/11/06 01:33:00 uwe Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -73,7 +73,8 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
#define MHZ(x) ((x) / 1000000), (((x) % 1000000) / 1000)
printf(": HITACHI SH%d %d.%02d MHz PCLOCK %d.%02d MHz\n",
aprint_naive("\n");
aprint_normal(": SH%d %d.%02d MHz PCLOCK %d.%02d MHz\n",
CPU_IS_SH3 ? 3 : 4,
MHZ(sh_clock_get_cpuclock()),
MHZ(sh_clock_get_pclock()));

18
sys/arch/sh3/sh3/mmu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mmu.c,v 1.15 2006/02/12 02:30:55 uwe Exp $ */
/* $NetBSD: mmu.c,v 1.16 2007/11/06 01:33:00 uwe Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mmu.c,v 1.15 2006/02/12 02:30:55 uwe Exp $");
__KERNEL_RCSID(0, "$NetBSD: mmu.c,v 1.16 2007/11/06 01:33:00 uwe Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -87,21 +87,23 @@ sh_mmu_information(void)
uint32_t r;
#ifdef SH3
if (CPU_IS_SH3) {
printf("cpu0: 4-way set-associative 128 TLB entries\n");
aprint_normal("cpu0: 4-way set-associative 128 TLB entries\n");
r = _reg_read_4(SH3_MMUCR);
printf("cpu0: %s mode, %s virtual storage mode\n",
aprint_normal("cpu0: %s mode, %s virtual storage mode\n",
r & SH3_MMUCR_IX ? "ASID+VPN" : "VPN",
r & SH3_MMUCR_SV ? "single" : "multiple");
}
#endif
#ifdef SH4
if (CPU_IS_SH4) {
printf("cpu0: full-associative 4 ITLB, 64 UTLB entries\n");
aprint_normal("cpu0: full-associative"
" 4 ITLB, 64 UTLB entries\n");
r = _reg_read_4(SH4_MMUCR);
printf("cpu0: %s virtual storage mode, SQ access: kernel%s, ",
aprint_normal("cpu0: %s virtual storage mode,"
" SQ access: kernel%s,"
" wired %d\n",
r & SH3_MMUCR_SV ? "single" : "multiple",
r & SH4_MMUCR_SQMD ? "" : "/user");
printf("wired %d\n",
r & SH4_MMUCR_SQMD ? "" : "/user",
(r & SH4_MMUCR_URB_MASK) >> SH4_MMUCR_URB_SHIFT);
}
#endif