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sun4v: Added handling of trap type 0x034 (address alignment error) + fixed typo mmfsa -> mmufsa. Verified for both sun4u and sun4v using qemu.

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This commit is contained in:
palle 2017-02-10 23:26:23 +00:00
parent 20f5a8dc9c
commit 88429e4286
7 changed files with 43 additions and 23 deletions
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4
sys/arch/sparc64/include/cpu.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.122 2016/06/25 13:52:04 palle Exp $ */
/* $NetBSD: cpu.h,v 1.123 2017/02/10 23:26:23 palle Exp $ */
/*
* Copyright (c) 1992, 1993
@ -185,7 +185,7 @@ struct cpu_info {
* Will be initialized to the physical address of the bottom of
* the interrupt stack.
*/
paddr_t ci_mmfsa;
paddr_t ci_mmufsa;
/*
* sun4v mondo control fields

13
sys/arch/sparc64/include/hypervisor.h
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@ -1,4 +1,4 @@
/* $NetBSD: hypervisor.h,v 1.5 2014/09/24 18:32:10 palle Exp $ */
/* $NetBSD: hypervisor.h,v 1.6 2017/02/10 23:26:23 palle Exp $ */
/* $OpenBSD: hypervisor.h,v 1.14 2011/06/26 17:23:46 kettenis Exp $ */
/*
@ -92,6 +92,17 @@ struct tsb_desc {
uint64_t td_reserved;
};
struct mmufsa {
uint64_t ift; /* instruction fault type */
uint64_t ifa; /* instruction fault address */
uint64_t ifc; /* instruction fault context */
uint64_t reserved1[5]; /* reserved */
uint64_t dft; /* data fault type */
uint64_t dfa; /* data fault address */
uint64_t dfc; /* data fault context */
uint64_t reserved2[5]; /* reserved */
};
int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr);
int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr);
#endif

6
sys/arch/sparc64/sparc64/cpu.c
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@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.129 2016/12/28 19:16:25 martin Exp $ */
/* $NetBSD: cpu.c,v 1.130 2017/02/10 23:26:23 palle Exp $ */
/*
* Copyright (c) 1996
@ -52,7 +52,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.129 2016/12/28 19:16:25 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.130 2017/02/10 23:26:23 palle Exp $");
#include "opt_multiprocessor.h"
@ -355,7 +355,7 @@ alloc_cpuinfo(u_int cpu_node)
cpi->ci_paddr = pa0;
cpi->ci_self = cpi;
if (CPU_ISSUN4V)
cpi->ci_mmfsa = pa0;
cpi->ci_mmufsa = pa0;
cpi->ci_node = cpu_node;
cpi->ci_idepth = -1;
memset(cpi->ci_intrpending, -1, sizeof(cpi->ci_intrpending));

4
sys/arch/sparc64/sparc64/genassym.cf
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@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.80 2017/01/27 21:35:38 palle Exp $
# $NetBSD: genassym.cf,v 1.81 2017/02/10 23:26:23 palle Exp $
#
# Copyright (c) 1997 The NetBSD Foundation, Inc.
@ -181,7 +181,7 @@ define CI_TICK_IH offsetof(struct cpu_info, ci_tick_ih)
define CI_CTXBUSY offsetof(struct cpu_info, ci_ctxbusy)
define CI_TSB_DMMU offsetof(struct cpu_info, ci_tsb_dmmu)
define CI_TSB_IMMU offsetof(struct cpu_info, ci_tsb_immu)
define CI_MMFSA offsetof(struct cpu_info, ci_mmfsa)
define CI_MMUFSA offsetof(struct cpu_info, ci_mmufsa)
define CI_TSB_DESC offsetof(struct cpu_info, ci_tsb_desc)
define CI_CPUMQ offsetof(struct cpu_info, ci_cpumq)
define CI_DEVMQ offsetof(struct cpu_info, ci_devmq)

10
sys/arch/sparc64/sparc64/locore.s
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@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.407 2017/01/30 21:24:33 palle Exp $ */
/* $NetBSD: locore.s,v 1.408 2017/02/10 23:26:23 palle Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@ -213,8 +213,8 @@
/* Misc. sun4v macros */
.macro GET_MMFSA reg
sethi %hi(CPUINFO_VA + CI_MMFSA), \reg
LDPTR [\reg + %lo(CPUINFO_VA + CI_MMFSA)], \reg
sethi %hi(CPUINFO_VA + CI_MMUFSA), \reg
LDPTR [\reg + %lo(CPUINFO_VA + CI_MMUFSA)], \reg
.endm
.macro GET_CTXBUSY reg
@ -1083,7 +1083,9 @@ _C_LABEL(trapbase_sun4v):
CLEANWIN0 ! 0x24-0x27 = clean window
sun4v_trap_entry 9 ! 0x028-0x030
VTRAP(T_DATA_MMU_MISS, sun4v_dtsb_miss) ! 0x031 = data MMU miss
sun4v_trap_entry 15 ! 0x032-0x040
sun4v_trap_entry 2 ! 0x032-0x033
TRAP(T_ALIGN) ! 0x034 = address alignment error
sun4v_trap_entry 12 ! 0x035-0x040
HARDINT4V(1) ! 0x041 = level 1 interrupt
HARDINT4V(2) ! 0x042 = level 2 interrupt
HARDINT4V(3) ! 0x043 = level 3 interrupt

6
sys/arch/sparc64/sparc64/pmap.c
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@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.306 2016/12/28 19:16:25 martin Exp $ */
/* $NetBSD: pmap.c,v 1.307 2017/02/10 23:26:23 palle Exp $ */
/*
*
* Copyright (C) 1996-1999 Eduardo Horvath.
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.306 2016/12/28 19:16:25 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.307 2017/02/10 23:26:23 palle Exp $");
#undef NO_VCACHE /* Don't forget the locked TLB in dostart */
#define HWREF
@ -1202,7 +1202,7 @@ pmap_bootstrap(u_long kernelstart, u_long kernelend)
cpus->ci_spinup = main; /* Call main when we're running. */
cpus->ci_paddr = cpu0paddr;
if (CPU_ISSUN4V) {
cpus->ci_mmfsa = cpu0paddr;
cpus->ci_mmufsa = cpu0paddr;
cpus->ci_tsb_desc = NULL;
}
cpus->ci_cpcb = (struct pcb *)u0va;

15
sys/arch/sparc64/sparc64/trap.c
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@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.184 2016/07/07 06:55:38 msaitoh Exp $ */
/* $NetBSD: trap.c,v 1.185 2017/02/10 23:26:23 palle Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath. All rights reserved.
@ -50,7 +50,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.184 2016/07/07 06:55:38 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.185 2017/02/10 23:26:23 palle Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@ -729,15 +729,22 @@ badtrap:
case T_LDDF_ALIGN:
case T_STDF_ALIGN:
{
int64_t dsfsr, dsfar=0;
int64_t dsfsr = 0, dsfar = 0;
#ifdef DEBUG
int64_t isfsr;
int64_t isfsr = 0;
#endif
if (!CPU_ISSUN4V) {
dsfsr = ldxa(SFSR, ASI_DMMU);
if (dsfsr & SFSR_FV)
dsfar = ldxa(SFAR, ASI_DMMU);
} else {
uint8_t* mmu_fsa_dfa = (uint8_t*)cpus->ci_mmufsa + offsetof(struct mmufsa, dfa);
dsfar = ldxa((paddr_t)mmu_fsa_dfa, ASI_PHYS_CACHED);
}
#ifdef DEBUG
if (!CPU_ISSUN4V) {
isfsr = ldxa(SFSR, ASI_IMMU);
}
#endif
/*
* If we're busy doing copyin/copyout continue