sync with OpenBSD-current (many bugfixes, add some devices)
if_msk.c: rev. 1.42 if_mskvar.h rev. 1.3 if_skreg.h rev. 1.41
This commit is contained in:
msaitoh
parent
0f1f665622
commit
874e8bcee6
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@ -1,5 +1,5 @@
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/* $NetBSD: if_msk.c,v 1.4 2007/01/05 09:23:41 msaitoh Exp $ */
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/* $OpenBSD: if_msk.c,v 1.11 2006/08/17 22:07:40 brad Exp $ */
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/* $NetBSD: if_msk.c,v 1.5 2007/01/30 11:34:38 msaitoh Exp $ */
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/* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */
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/*
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* Copyright (c) 1997, 1998, 1999, 2000
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@ -125,15 +125,14 @@ int msk_init_tx_ring(struct sk_if_softc *);
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void msk_update_int_mod(struct sk_softc *);
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int msk_marv_miibus_readreg(struct device *, int, int);
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void msk_marv_miibus_writereg(struct device *, int, int, int);
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void msk_marv_miibus_statchg(struct device *);
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int msk_miibus_readreg(struct device *, int, int);
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void msk_miibus_writereg(struct device *, int, int, int);
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void msk_miibus_statchg(struct device *);
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u_int32_t msk_yukon_hash(caddr_t);
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void msk_setfilt(struct sk_if_softc *, caddr_t, int);
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void msk_setmulti(struct sk_if_softc *);
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void msk_setpromisc(struct sk_if_softc *);
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void msk_yukon_tick(void *);
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void msk_tick(void *);
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/* #define MSK_DEBUG 1 */
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#ifdef MSK_DEBUG
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@ -157,21 +156,32 @@ static const struct msk_product {
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pci_vendor_id_t msk_vendor;
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pci_product_id_t msk_product;
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} msk_products[] = {
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{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX },
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{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX },
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{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X },
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{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_3 },
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{ PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX },
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{ PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }
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};
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@ -213,20 +223,12 @@ sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
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}
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int
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msk_marv_miibus_readreg(struct device *dev, int phy, int reg)
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msk_miibus_readreg(struct device *dev, int phy, int reg)
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{
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struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
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u_int16_t val;
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int i;
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if (phy != 0 ||
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(sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
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sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
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DPRINTFN(9, ("msk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
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phy, reg));
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return (0);
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}
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SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
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YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
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@ -243,24 +245,24 @@ msk_marv_miibus_readreg(struct device *dev, int phy, int reg)
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return (0);
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}
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DPRINTFN(9, ("msk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
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DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i,
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SK_TIMEOUT));
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val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
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DPRINTFN(9, ("msk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
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DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
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phy, reg, val));
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return (val);
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}
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void
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msk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
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msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
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{
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struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
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int i;
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DPRINTFN(9, ("msk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
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DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n",
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phy, reg, val));
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SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
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@ -278,23 +280,49 @@ msk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
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}
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void
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msk_marv_miibus_statchg(struct device *dev)
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msk_miibus_statchg(struct device *dev)
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{
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DPRINTFN(9, ("msk_marv_miibus_statchg: gpcr=%x\n",
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struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
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struct mii_data *mii = &sc_if->sk_mii;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int gpcr;
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gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR);
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gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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/* Set speed. */
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gpcr |= YU_GPCR_SPEED_DIS;
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switch (IFM_SUBTYPE(mii->mii_media_active)) {
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case IFM_1000_SX:
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case IFM_1000_LX:
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case IFM_1000_CX:
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case IFM_1000_T:
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gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED);
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break;
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case IFM_100_TX:
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gpcr |= YU_GPCR_SPEED;
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break;
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}
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/* Set duplex. */
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gpcr |= YU_GPCR_DPLX_DIS;
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
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gpcr |= YU_GPCR_DUPLEX;
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/* Disable flow control. */
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gpcr |= YU_GPCR_FCTL_DIS;
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gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS);
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}
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SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr);
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DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n",
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SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR)));
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}
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#define HASH_BITS 6
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u_int32_t
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msk_yukon_hash(caddr_t addr)
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{
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u_int32_t crc;
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crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
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return (crc & ((1 << HASH_BITS) - 1));
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}
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void
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msk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
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{
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@ -336,7 +364,8 @@ allmulti:
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ifp->if_flags |= IFF_ALLMULTI;
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goto allmulti;
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}
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h = msk_yukon_hash(enm->enm_addrlo);
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h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
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((1 << HASH_BITS) - 1);
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if (h < 32)
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hashes[0] |= (1 << h);
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else
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@ -562,16 +591,13 @@ msk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
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entry = malloc(sizeof(struct sk_jpool_entry),
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M_DEVBUF, M_NOWAIT);
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if (entry == NULL) {
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sc_if->sk_cdata.sk_jumbo_buf = NULL;
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aprint_error(": no memory for jumbo buffer queue!");
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error = ENOBUFS;
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goto out;
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}
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entry->slot = i;
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if (i)
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LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
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entry, jpool_entries);
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else
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LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead,
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LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
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entry, jpool_entries);
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}
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out:
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@ -631,7 +657,6 @@ msk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg)
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panic("msk_jfree: can't find softc pointer!");
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/* calculate the slot this buffer belongs to */
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i = ((vaddr_t)buf
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- (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
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@ -659,7 +684,6 @@ msk_ifmedia_upd(struct ifnet *ifp)
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{
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struct sk_if_softc *sc_if = ifp->if_softc;
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msk_init(ifp);
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mii_mediachg(&sc_if->sk_mii);
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return (0);
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}
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@ -688,6 +712,16 @@ msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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s = splnet();
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switch(command) {
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case SIOCSIFMTU:
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if (ifr->ifr_mtu < ETHERMIN)
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return EINVAL;
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else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) {
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if (ifr->ifr_mtu > SK_JUMBO_MTU)
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error = EINVAL;
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} else if (ifr->ifr_mtu > ETHERMTU)
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error = EINVAL;
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ifp->if_mtu = ifr->ifr_mtu;
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break;
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case SIOCGIFMEDIA:
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case SIOCSIFMEDIA:
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DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA\n"));
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@ -718,7 +752,7 @@ msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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void
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msk_update_int_mod(struct sk_softc *sc)
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{
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u_int32_t sk_imtimer_ticks;
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u_int32_t imtimer_ticks;
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/*
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* Configure interrupt moderation. The moderation timer
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@ -731,10 +765,10 @@ msk_update_int_mod(struct sk_softc *sc)
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*/
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switch (sc->sk_type) {
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case SK_YUKON_EC:
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sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
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imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
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break;
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default:
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sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
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imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
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}
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aprint_verbose("%s: interrupt moderation is %d us\n",
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sc->sk_dev.dv_xname, sc->sk_int_mod);
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@ -776,20 +810,44 @@ mskc_probe(struct device *parent, struct cfdata *match,
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*/
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void msk_reset(struct sk_softc *sc)
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{
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u_int32_t sk_imtimer_ticks;
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u_int32_t imtimer_ticks, reg1;
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int reg;
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DPRINTFN(2, ("msk_reset\n"));
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CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
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CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
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CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
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DELAY(1000);
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CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
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DELAY(2);
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CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
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sk_win_write_1(sc, SK_TESTCTL1, 2);
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reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
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if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
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reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
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else
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reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
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sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
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if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
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sk_win_write_1(sc, SK_Y2_CLKGATE,
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SK_Y2_CLKGATE_LINK1_GATE_DIS |
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SK_Y2_CLKGATE_LINK2_GATE_DIS |
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SK_Y2_CLKGATE_LINK1_CORE_DIS |
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SK_Y2_CLKGATE_LINK2_CORE_DIS |
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SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS);
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else
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sk_win_write_1(sc, SK_Y2_CLKGATE, 0);
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CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
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CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);
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DELAY(1000);
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CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
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CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);
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sk_win_write_1(sc, SK_TESTCTL1, 1);
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DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
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DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n",
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@ -817,6 +875,9 @@ void msk_reset(struct sk_softc *sc)
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sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
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for (reg = SK_TO0;reg <= SK_TO11; reg++)
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sk_win_write_1(sc, reg, 36);
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sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET);
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for (reg = SK_TO0;reg <= SK_TO11; reg++)
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sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
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/*
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* Configure interrupt moderation. The moderation timer
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@ -831,10 +892,10 @@ void msk_reset(struct sk_softc *sc)
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case SK_YUKON_EC:
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case SK_YUKON_XL:
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case SK_YUKON_FE:
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sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
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imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
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break;
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default:
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sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
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imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
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}
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/* Reset status ring. */
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@ -956,23 +1017,6 @@ msk_attach(struct device *parent, struct device *self, void *aux)
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sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
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sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
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/* Read and save PHY type */
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sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
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/* Set PHY address */
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if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
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sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
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/* not initialized, punt */
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sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
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sc->sk_coppertype = 1;
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}
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sc_if->sk_phyaddr = SK_PHYADDR_MARV;
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if (!(sc->sk_coppertype))
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sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
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/* Allocate the descriptor queues. */
|
||||
if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data),
|
||||
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
|
||||
|
|
@ -1028,14 +1072,14 @@ msk_attach(struct device *parent, struct device *self, void *aux)
|
|||
DPRINTFN(2, ("msk_attach: 1\n"));
|
||||
|
||||
sc_if->sk_mii.mii_ifp = ifp;
|
||||
sc_if->sk_mii.mii_readreg = msk_marv_miibus_readreg;
|
||||
sc_if->sk_mii.mii_writereg = msk_marv_miibus_writereg;
|
||||
sc_if->sk_mii.mii_statchg = msk_marv_miibus_statchg;
|
||||
sc_if->sk_mii.mii_readreg = msk_miibus_readreg;
|
||||
sc_if->sk_mii.mii_writereg = msk_miibus_writereg;
|
||||
sc_if->sk_mii.mii_statchg = msk_miibus_statchg;
|
||||
|
||||
ifmedia_init(&sc_if->sk_mii.mii_media, 0,
|
||||
msk_ifmedia_upd, msk_ifmedia_sts);
|
||||
mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
|
||||
MII_OFFSET_ANY, 0);
|
||||
MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG);
|
||||
if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) {
|
||||
aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname);
|
||||
ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL,
|
||||
|
|
@ -1045,7 +1089,7 @@ msk_attach(struct device *parent, struct device *self, void *aux)
|
|||
ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO);
|
||||
|
||||
callout_init(&sc_if->sk_tick_ch);
|
||||
callout_setfunc(&sc_if->sk_tick_ch, msk_yukon_tick, sc_if);
|
||||
callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if);
|
||||
callout_schedule(&sc_if->sk_tick_ch, hz);
|
||||
|
||||
/*
|
||||
|
|
@ -1165,7 +1209,7 @@ mskc_attach(struct device *parent, struct device *self, void *aux)
|
|||
sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
|
||||
|
||||
/* bail out here if chip is not recognized */
|
||||
if (!(SK_IS_YUKON(sc))) {
|
||||
if (!(SK_IS_YUKON2(sc))) {
|
||||
aprint_error(": unknown chip type: %d\n", sc->sk_type);
|
||||
goto fail_1;
|
||||
}
|
||||
|
|
@ -1232,31 +1276,21 @@ mskc_attach(struct device *parent, struct device *self, void *aux)
|
|||
sc->sk_ramsize, sc->sk_ramsize / 1024,
|
||||
sc->sk_rboff));
|
||||
|
||||
/* Read and save physical media type */
|
||||
sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
|
||||
|
||||
if (sc->sk_pmd == 'T' || sc->sk_pmd == '1' ||
|
||||
(SK_IS_YUKON2(sc) && !(sc->sk_pmd == 'L' ||
|
||||
sc->sk_pmd == 'S')))
|
||||
sc->sk_coppertype = 1;
|
||||
else
|
||||
sc->sk_coppertype = 0;
|
||||
|
||||
switch (sc->sk_type) {
|
||||
case SK_YUKON_XL:
|
||||
sc->sk_name = "Marvell Yukon-2 XL";
|
||||
sc->sk_name = "Yukon-2 XL";
|
||||
break;
|
||||
case SK_YUKON_EC_U:
|
||||
sc->sk_name = "Marvell Yukon-2 EC Ultra";
|
||||
sc->sk_name = "Yukon-2 EC Ultra";
|
||||
break;
|
||||
case SK_YUKON_EC:
|
||||
sc->sk_name = "Marvell Yukon-2 EC";
|
||||
sc->sk_name = "Yukon-2 EC";
|
||||
break;
|
||||
case SK_YUKON_FE:
|
||||
sc->sk_name = "Marvell Yukon-2 FE";
|
||||
sc->sk_name = "Yukon-2 FE";
|
||||
break;
|
||||
default:
|
||||
sc->sk_name = "Marvell Yukon (Unknown)";
|
||||
sc->sk_name = "Yukon (Unknown)";
|
||||
}
|
||||
|
||||
if (sc->sk_type == SK_YUKON_XL) {
|
||||
|
|
@ -1313,7 +1347,6 @@ mskc_attach(struct device *parent, struct device *self, void *aux)
|
|||
aprint_normal(" rev. %s", revstr);
|
||||
aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr);
|
||||
|
||||
|
||||
sc->sk_macs = 1;
|
||||
|
||||
hw = sk_win_read_1(sc, SK_Y2_HWRES);
|
||||
|
|
@ -1390,7 +1423,7 @@ msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
|
|||
{
|
||||
struct sk_softc *sc = sc_if->sk_softc;
|
||||
struct msk_tx_desc *f = NULL;
|
||||
u_int32_t frag, cur, cnt = 0;
|
||||
u_int32_t frag, cur;
|
||||
int i;
|
||||
struct sk_txmap_entry *entry;
|
||||
bus_dmamap_t txmap;
|
||||
|
|
@ -1422,6 +1455,12 @@ msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
|
|||
return (ENOBUFS);
|
||||
}
|
||||
|
||||
if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) {
|
||||
DPRINTFN(2, ("msk_encap: too few descriptors free\n"));
|
||||
bus_dmamap_unload(sc->sc_dmatag, txmap);
|
||||
return (ENOBUFS);
|
||||
}
|
||||
|
||||
DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
|
||||
|
||||
/* Sync the DMA map. */
|
||||
|
|
@ -1429,21 +1468,16 @@ msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
|
|||
BUS_DMASYNC_PREWRITE);
|
||||
|
||||
for (i = 0; i < txmap->dm_nsegs; i++) {
|
||||
if ((MSK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) {
|
||||
DPRINTFN(2, ("msk_encap: too few descriptors free\n"));
|
||||
return (ENOBUFS);
|
||||
}
|
||||
f = &sc_if->sk_rdata->sk_tx_ring[frag];
|
||||
f->sk_addr = htole32(txmap->dm_segs[i].ds_addr);
|
||||
f->sk_len = htole16(txmap->dm_segs[i].ds_len);
|
||||
f->sk_ctl = 0;
|
||||
if (cnt == 0)
|
||||
if (i == 0)
|
||||
f->sk_opcode = SK_Y2_TXOPC_PACKET;
|
||||
else
|
||||
f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN;
|
||||
cur = frag;
|
||||
SK_INC(frag, MSK_TX_RING_CNT);
|
||||
cnt++;
|
||||
}
|
||||
|
||||
sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
|
||||
|
|
@ -1462,7 +1496,7 @@ msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
|
|||
MSK_CDTXSYNC(sc_if, *txidx, 1,
|
||||
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
||||
|
||||
sc_if->sk_cdata.sk_tx_cnt += cnt;
|
||||
sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs;
|
||||
|
||||
#ifdef MSK_DEBUG
|
||||
if (mskdebug >= 2) {
|
||||
|
|
@ -1655,27 +1689,32 @@ msk_txeof(struct sk_if_softc *sc_if)
|
|||
struct sk_softc *sc = sc_if->sk_softc;
|
||||
struct msk_tx_desc *cur_tx;
|
||||
struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
|
||||
u_int32_t idx, sk_ctl;
|
||||
u_int32_t idx, reg, sk_ctl;
|
||||
struct sk_txmap_entry *entry;
|
||||
|
||||
DPRINTFN(2, ("msk_txeof\n"));
|
||||
|
||||
if (sc_if->sk_port == SK_PORT_A)
|
||||
reg = SK_STAT_BMU_TXA1_RIDX;
|
||||
else
|
||||
reg = SK_STAT_BMU_TXA2_RIDX;
|
||||
|
||||
/*
|
||||
* Go through our tx ring and free mbufs for those
|
||||
* frames that have been sent.
|
||||
*/
|
||||
idx = sc_if->sk_cdata.sk_tx_cons;
|
||||
while (idx != sk_win_read_2(sc, SK_STAT_BMU_TXA1_RIDX)) {
|
||||
while (idx != sk_win_read_2(sc, reg)) {
|
||||
MSK_CDTXSYNC(sc_if, idx, 1,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
|
||||
cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
|
||||
sk_ctl = letoh32(cur_tx->sk_ctl);
|
||||
sk_ctl = cur_tx->sk_ctl;
|
||||
#ifdef MSK_DEBUG
|
||||
if (mskdebug >= 2)
|
||||
msk_dump_txdesc(cur_tx, idx);
|
||||
#endif
|
||||
if (sk_ctl & SK_TXCTL_LASTFRAG)
|
||||
if (sk_ctl & SK_Y2_TXCTL_LASTFRAG)
|
||||
ifp->if_opackets++;
|
||||
if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
|
||||
entry = sc_if->sk_cdata.sk_tx_map[idx];
|
||||
|
|
@ -1703,7 +1742,7 @@ msk_txeof(struct sk_if_softc *sc_if)
|
|||
}
|
||||
|
||||
void
|
||||
msk_yukon_tick(void *xsc_if)
|
||||
msk_tick(void *xsc_if)
|
||||
{
|
||||
struct sk_if_softc *sc_if = xsc_if;
|
||||
struct mii_data *mii = &sc_if->sk_mii;
|
||||
|
|
@ -1741,7 +1780,6 @@ msk_intr(void *xsc)
|
|||
struct ifnet *ifp0 = NULL, *ifp1 = NULL;
|
||||
int claimed = 0;
|
||||
u_int32_t status;
|
||||
u_int16_t idx;
|
||||
struct msk_status_desc *cur_st;
|
||||
|
||||
status = CSR_READ_4(sc, SK_Y2_ISSR2);
|
||||
|
|
@ -1767,13 +1805,13 @@ msk_intr(void *xsc)
|
|||
msk_intr_yukon(sc_if1);
|
||||
}
|
||||
|
||||
idx = CSR_READ_2(sc, SK_STAT_BMU_PUTIDX);
|
||||
while (sc->sk_status_idx != idx) {
|
||||
MSK_CDSTSYNC(sc, sc->sk_status_idx,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
MSK_CDSTSYNC(sc, sc->sk_status_idx,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
cur_st = &sc->sk_status_ring[sc->sk_status_idx];
|
||||
|
||||
cur_st = &sc->sk_status_ring[sc->sk_status_idx];
|
||||
switch (cur_st->sk_opcode & ~SK_Y2_STOPC_OWN) {
|
||||
while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) {
|
||||
cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN;
|
||||
switch (cur_st->sk_opcode) {
|
||||
case SK_Y2_STOPC_RXSTAT:
|
||||
msk_rxeof(sc->sk_if[cur_st->sk_link],
|
||||
letoh16(cur_st->sk_len),
|
||||
|
|
@ -1783,14 +1821,20 @@ msk_intr(void *xsc)
|
|||
sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod);
|
||||
break;
|
||||
case SK_Y2_STOPC_TXSTAT:
|
||||
msk_txeof(sc->sk_if[cur_st->sk_link]);
|
||||
if (sc_if0)
|
||||
msk_txeof(sc_if0);
|
||||
if (sc_if1)
|
||||
msk_txeof(sc_if1);
|
||||
break;
|
||||
default:
|
||||
aprint_error("opcode=0x%x\n", cur_st->sk_opcode);
|
||||
break;
|
||||
}
|
||||
SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT);
|
||||
idx = CSR_READ_2(sc, SK_STAT_BMU_PUTIDX);
|
||||
|
||||
MSK_CDSTSYNC(sc, sc->sk_status_idx,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
cur_st = &sc->sk_status_ring[sc->sk_status_idx];
|
||||
}
|
||||
|
||||
if (status & SK_Y2_IMR_BMU) {
|
||||
|
|
@ -1819,7 +1863,7 @@ msk_intr(void *xsc)
|
|||
void
|
||||
msk_init_yukon(struct sk_if_softc *sc_if)
|
||||
{
|
||||
u_int32_t phy, v;
|
||||
u_int32_t v;
|
||||
u_int16_t reg;
|
||||
struct sk_softc *sc;
|
||||
int i;
|
||||
|
|
@ -1832,29 +1876,13 @@ msk_init_yukon(struct sk_if_softc *sc_if)
|
|||
DPRINTFN(6, ("msk_init_yukon: 1\n"));
|
||||
|
||||
/* GMAC and GPHY Reset */
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
|
||||
DELAY(1000);
|
||||
|
||||
DPRINTFN(6, ("msk_init_yukon: 2\n"));
|
||||
|
||||
#if 0
|
||||
phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
|
||||
SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
|
||||
#else
|
||||
phy = SK_GPHY_ENA_PAUSE;
|
||||
#endif
|
||||
|
||||
if (sc->sk_coppertype)
|
||||
phy |= SK_GPHY_COPPER;
|
||||
else
|
||||
phy |= SK_GPHY_FIBER;
|
||||
|
||||
DPRINTFN(3, ("msk_init_yukon: phy=%#x\n", phy));
|
||||
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
|
||||
DELAY(1000);
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
|
||||
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
|
||||
SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
|
||||
|
||||
|
|
@ -1893,9 +1921,14 @@ msk_init_yukon(struct sk_if_softc *sc_if)
|
|||
|
||||
/* serial mode register */
|
||||
DPRINTFN(6, ("msk_init_yukon: 9\n"));
|
||||
SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
|
||||
YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO |
|
||||
YU_SMR_IPG_DATA(0x1e));
|
||||
reg = YU_SMR_DATA_BLIND(0x1c) |
|
||||
YU_SMR_MFL_VLAN |
|
||||
YU_SMR_IPG_DATA(0x1e);
|
||||
|
||||
if (sc->sk_type != SK_YUKON_FE)
|
||||
reg |= YU_SMR_MFL_JUMBO;
|
||||
|
||||
SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
|
||||
|
||||
DPRINTFN(6, ("msk_init_yukon: 10\n"));
|
||||
/* Setup Yukon's address */
|
||||
|
|
@ -1965,7 +1998,7 @@ msk_init(struct ifnet *ifp)
|
|||
struct sk_softc *sc = sc_if->sk_softc;
|
||||
struct mii_data *mii = &sc_if->sk_mii;
|
||||
int s;
|
||||
uint32_t imr, sk_imtimer_ticks;
|
||||
uint32_t imr, imtimer_ticks;
|
||||
|
||||
|
||||
DPRINTFN(2, ("msk_init\n"));
|
||||
|
|
@ -2037,10 +2070,10 @@ msk_init(struct ifnet *ifp)
|
|||
/* Set interrupt moderation if changed via sysctl. */
|
||||
switch (sc->sk_type) {
|
||||
case SK_YUKON_EC:
|
||||
sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
|
||||
imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
|
||||
break;
|
||||
default:
|
||||
sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
|
||||
imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
|
||||
}
|
||||
imr = sk_win_read_4(sc, SK_IMTIMERINIT);
|
||||
if (imr != SK_IM_USECS(sc->sk_int_mod)) {
|
||||
|
|
@ -2119,7 +2152,7 @@ msk_stop(struct ifnet *ifp, int disable)
|
|||
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
|
||||
SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
|
||||
SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
|
||||
SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
|
||||
SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP);
|
||||
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
|
||||
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* $OpenBSD: if_mskvar.h,v 1.1 2006/08/16 21:06:23 kettenis Exp $ */
|
||||
/* $NetBSD: if_mskvar.h,v 1.1 2006/09/09 16:17:50 riz Exp $ */
|
||||
/* $OpenBSD: if_mskvar.h,v 1.3 2006/12/28 16:34:42 kettenis Exp $ */
|
||||
/* $NetBSD: if_mskvar.h,v 1.2 2007/01/30 11:34:39 msaitoh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2003 The NetBSD Foundation, Inc.
|
||||
|
|
@ -199,8 +199,6 @@ struct sk_softc {
|
|||
bus_space_handle_t sk_bhandle; /* bus space handle */
|
||||
bus_space_tag_t sk_btag; /* bus space tag */
|
||||
void *sk_intrhand; /* irq handler handle */
|
||||
u_int8_t sk_coppertype;
|
||||
u_int8_t sk_pmd; /* physical media type */
|
||||
u_int8_t sk_type;
|
||||
u_int8_t sk_rev;
|
||||
u_int8_t sk_macs; /* # of MACs */
|
||||
|
|
@ -232,8 +230,6 @@ struct sk_if_softc {
|
|||
u_int32_t sk_rx_ramend;
|
||||
u_int32_t sk_tx_ramstart;
|
||||
u_int32_t sk_tx_ramend;
|
||||
u_int8_t sk_phytype;
|
||||
int sk_phyaddr;
|
||||
int sk_cnt;
|
||||
int sk_link;
|
||||
struct callout sk_tick_ch;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: if_skreg.h,v 1.8 2006/09/09 16:17:50 riz Exp $ */
|
||||
/* $NetBSD: if_skreg.h,v 1.9 2007/01/30 11:34:39 msaitoh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2003 The NetBSD Foundation, Inc.
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
*/
|
||||
/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */
|
||||
/* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */
|
||||
/* $OpenBSD: if_skreg.h,v 1.37 2006/08/16 21:06:23 kettenis Exp $ */
|
||||
/* $OpenBSD: if_skreg.h,v 1.41 2006/11/23 21:56:32 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997, 1998, 1999, 2000
|
||||
|
|
@ -172,6 +172,7 @@
|
|||
#define SK_RAP 0x0000
|
||||
#define SK_CSR 0x0004
|
||||
#define SK_LED 0x0006
|
||||
/* XXX 0x0007 B0_POWER_CTRL */
|
||||
#define SK_ISR 0x0008 /* interrupt source */
|
||||
#define SK_IMR 0x000C /* interrupt mask */
|
||||
#define SK_IESR 0x0010 /* interrupt hardware error source */
|
||||
|
|
@ -353,9 +354,9 @@
|
|||
#define SK_CONFIG 0x011A
|
||||
#define SK_CHIPVER 0x011B
|
||||
#define SK_EPROM0 0x011C
|
||||
#define SK_EPROM1 0x011D
|
||||
#define SK_EPROM1 0x011D /* yukon/genesis */
|
||||
#define SK_Y2_CLKGATE 0x011D /* yukon 2 */
|
||||
#define SK_EPROM2 0x011E
|
||||
#define SK_EPROM2 0x011E /* yukon/genesis */
|
||||
#define SK_Y2_HWRES 0x011E /* yukon 2 */
|
||||
#define SK_EPROM3 0x011F
|
||||
#define SK_EP_ADDR 0x0120
|
||||
|
|
@ -385,7 +386,7 @@
|
|||
#define SK_BLNKSTS 0x0179
|
||||
#define SK_BLNKTST 0x017A
|
||||
|
||||
/* values for SK_CHIPVER */
|
||||
/* Values for SK_CHIPVER */
|
||||
#define SK_GENESIS 0x0A
|
||||
#define SK_YUKON 0xB0
|
||||
#define SK_YUKON_LITE 0xB1
|
||||
|
|
@ -399,11 +400,11 @@
|
|||
#define SK_IS_GENESIS(sc) \
|
||||
((sc)->sk_type == SK_GENESIS)
|
||||
#define SK_IS_YUKON(sc) \
|
||||
((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_FE)
|
||||
((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_LP)
|
||||
#define SK_IS_YUKON2(sc) \
|
||||
((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE)
|
||||
|
||||
/* known revisions in SK_CONFIG */
|
||||
/* Known revisions in SK_CONFIG */
|
||||
#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach */
|
||||
#define SK_YUKON_LITE_REV_A1 0x3
|
||||
#define SK_YUKON_LITE_REV_A3 0x7
|
||||
|
|
@ -425,13 +426,15 @@
|
|||
#define SK_IMCTL_START 0x04
|
||||
|
||||
/* Number of ticks per usec for interrupt moderation */
|
||||
#define SK_IMTIMER_TICKS_GENESIS 54
|
||||
#define SK_IMTIMER_TICKS_YUKON 78
|
||||
#define SK_IMTIMER_TICKS_GENESIS 53
|
||||
#define SK_IMTIMER_TICKS_YUKON 156
|
||||
#define SK_IMTIMER_TICKS_YUKON_EC 125
|
||||
#define SK_IM_USECS(x) ((x) * sk_imtimer_ticks)
|
||||
#define SK_IMTIMER_TICKS_YUKON_FE 100
|
||||
#define SK_IMTIMER_TICKS_YUKON_XL 156
|
||||
#define SK_IM_USECS(x) ((x) * imtimer_ticks)
|
||||
|
||||
#define SK_IM_MIN 0
|
||||
#define SK_IM_DEFAULT 100
|
||||
#define SK_IM_DEFAULT 1000
|
||||
#define SK_IM_MAX 10000
|
||||
/*
|
||||
* The SK_EPROM0 register contains a byte that describes the
|
||||
|
|
@ -472,9 +475,9 @@
|
|||
#define SK_CONFIG_DIS_DSL_CLK 0x02
|
||||
|
||||
#define SK_PMD_1000BASETX_ALT 0x31
|
||||
#define SK_PMD_1000BASECX 0x43
|
||||
#define SK_PMD_1000BASELX 0x4C
|
||||
#define SK_PMD_1000BASESX 0x53
|
||||
#define SK_PMD_1000BASECX 0x43
|
||||
#define SK_PMD_1000BASETX 0x54
|
||||
|
||||
/* GPIO bits */
|
||||
|
|
@ -499,19 +502,19 @@
|
|||
#define SK_GPIO_DIR8 0x01000000
|
||||
#define SK_GPIO_DIR9 0x02000000
|
||||
|
||||
#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */
|
||||
#define SK_Y2_CLKGATE_LINK2_GATE_DIS 0x40 /* disable clock gate, 2 */
|
||||
#define SK_Y2_CLKGATE_LINK2_CORE_DIS 0x20 /* disable core clock, 2 */
|
||||
#define SK_Y2_CLKGATE_LINK2_PCI_DIS 0x10 /* disable pci clock, 2 */
|
||||
#define SK_Y2_CLKGATE_LINK1_INACTIVE 0x08 /* port 1 inactive */
|
||||
#define SK_Y2_CLKGATE_LINK1_GATE_DIS 0x04 /* disable clock gate, 1 */
|
||||
#define SK_Y2_CLKGATE_LINK1_CORE_DIS 0x02 /* disable core clock, 1 */
|
||||
#define SK_Y2_CLKGATE_LINK1_PCI_DIS 0x01 /* disable pci clock, 1 */
|
||||
#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */
|
||||
#define SK_Y2_CLKGATE_LINK2_GATE_DIS 0x40 /* disable clock gate, 2 */
|
||||
#define SK_Y2_CLKGATE_LINK2_CORE_DIS 0x20 /* disable core clock, 2 */
|
||||
#define SK_Y2_CLKGATE_LINK2_PCI_DIS 0x10 /* disable pci clock, 2 */
|
||||
#define SK_Y2_CLKGATE_LINK1_INACTIVE 0x08 /* port 1 inactive */
|
||||
#define SK_Y2_CLKGATE_LINK1_GATE_DIS 0x04 /* disable clock gate, 1 */
|
||||
#define SK_Y2_CLKGATE_LINK1_CORE_DIS 0x02 /* disable core clock, 1 */
|
||||
#define SK_Y2_CLKGATE_LINK1_PCI_DIS 0x01 /* disable pci clock, 1 */
|
||||
|
||||
#define SK_Y2_HWRES_LINK_1 0x01
|
||||
#define SK_Y2_HWRES_LINK_2 0x02
|
||||
#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
|
||||
#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
|
||||
#define SK_Y2_HWRES_LINK_1 0x01
|
||||
#define SK_Y2_HWRES_LINK_2 0x02
|
||||
#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
|
||||
#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
|
||||
|
||||
/* Block 3 Ram interface and MAC arbiter registers */
|
||||
#define SK_RAMADDR 0x0180
|
||||
|
|
@ -856,8 +859,6 @@
|
|||
#define SK_TXQA1_Y2_PREF_GETIDX 0x06E0
|
||||
#define SK_TXQA1_Y2_PREF_PUTIDX 0x06E4
|
||||
#define SK_TXQA1_Y2_PREF_FIFOWP 0x06F0
|
||||
#define SK_TXQA1_Y2_PREF_PUTIDX 0x06E4
|
||||
#define SK_TXQA1_Y2_PREF_FIFOWP 0x06F0
|
||||
#define SK_TXQA1_Y2_PREF_FIFORP 0x06F4
|
||||
#define SK_TXQA1_Y2_PREF_FIFOWM 0x06F8
|
||||
#define SK_TXQA1_Y2_PREF_FIFOLV 0x06FC
|
||||
|
|
@ -977,13 +978,13 @@
|
|||
(SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
|
||||
SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
|
||||
SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
|
||||
SK_TXBMU_DESC_UNRESET)
|
||||
SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
|
||||
|
||||
#define SK_TXBMU_OFFLINE \
|
||||
(SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
|
||||
SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
|
||||
SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
|
||||
SK_TXBMU_DESC_RESET)
|
||||
SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
|
||||
|
||||
/* Block 16 -- Receive RAMbuffer 1 */
|
||||
#define SK_RXRB1_START 0x0800
|
||||
|
|
@ -1047,12 +1048,12 @@
|
|||
#define SK_TXRBA2_LVL 0x0BA4
|
||||
#define SK_TXRBA2_CTLTST 0x0BA8
|
||||
|
||||
#define SK_RBCTL_RESET 0x00000001
|
||||
#define SK_RBCTL_UNRESET 0x00000002
|
||||
#define SK_RBCTL_OFF 0x00000004
|
||||
#define SK_RBCTL_ON 0x00000008
|
||||
#define SK_RBCTL_STORENFWD_OFF 0x00000010
|
||||
#define SK_RBCTL_STORENFWD_ON 0x00000020
|
||||
#define SK_RBCTL_RESET 0x01
|
||||
#define SK_RBCTL_UNRESET 0x02
|
||||
#define SK_RBCTL_OFF 0x04
|
||||
#define SK_RBCTL_ON 0x08
|
||||
#define SK_RBCTL_STORENFWD_OFF 0x10
|
||||
#define SK_RBCTL_STORENFWD_ON 0x20
|
||||
|
||||
/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
|
||||
#define SK_RXF1_END 0x0C00
|
||||
|
|
@ -1078,13 +1079,14 @@
|
|||
#define SK_RXMF1_END 0x0C40
|
||||
#define SK_RXMF1_THRESHOLD 0x0C44
|
||||
#define SK_RXMF1_CTRL_TEST 0x0C48
|
||||
#define SK_RXMF1_FLUSH_MASK 0x0C4C
|
||||
#define SK_RXMF1_FLUSH_MASK 0x0C4C
|
||||
#define SK_RXMF1_FLUSH_THRESHOLD 0x0C50
|
||||
#define SK_RXMF1_WRITE_PTR 0x0C60
|
||||
#define SK_RXMF1_WRITE_LEVEL 0x0C68
|
||||
#define SK_RXMF1_READ_PTR 0x0C70
|
||||
#define SK_RXMF1_READ_LEVEL 0x0C78
|
||||
|
||||
/* Receive MAC FIFO 1 Control/Test */
|
||||
#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
|
||||
#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
|
||||
#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
|
||||
|
|
@ -1092,8 +1094,8 @@
|
|||
#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
|
||||
#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
|
||||
#define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */
|
||||
#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */
|
||||
#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */
|
||||
#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */
|
||||
#define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */
|
||||
#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */
|
||||
#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
|
||||
#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
|
||||
|
|
@ -1161,7 +1163,7 @@
|
|||
#define SK_TXLED1_CTL 0x0D28
|
||||
#define SK_TXLED1_TST 0x0D29
|
||||
|
||||
/* Receive MAC FIFO 1 (Yukon Only) */
|
||||
/* Transmit MAC FIFO 1 (Yukon Only) */
|
||||
#define SK_TXMF1_END 0x0D40
|
||||
#define SK_TXMF1_THRESHOLD 0x0D44
|
||||
#define SK_TXMF1_CTRL_TEST 0x0D48
|
||||
|
|
@ -1172,6 +1174,7 @@
|
|||
#define SK_TXMF1_RESTART_PTR 0x0D74
|
||||
#define SK_TXMF1_READ_LEVEL 0x0D78
|
||||
|
||||
/* Transmit MAC FIFO Control/Test */
|
||||
#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
|
||||
#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
|
||||
#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
|
||||
|
|
@ -1229,9 +1232,11 @@
|
|||
#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */
|
||||
#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */
|
||||
|
||||
#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */
|
||||
#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */
|
||||
#define SK_DPT_TCTL_START 0x0002 /* Start Timer */
|
||||
#define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */
|
||||
|
||||
#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 8 bits */
|
||||
#define SK_DPT_TCTL_STOP 0x01 /* Stop Timer */
|
||||
#define SK_DPT_TCTL_START 0x02 /* Start Timer */
|
||||
|
||||
#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */
|
||||
#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */
|
||||
|
|
@ -1285,7 +1290,7 @@
|
|||
#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */
|
||||
#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */
|
||||
#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */
|
||||
#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */
|
||||
#define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */
|
||||
#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */
|
||||
#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */
|
||||
#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */
|
||||
|
|
@ -1365,7 +1370,15 @@
|
|||
/* Block 32-33 -- Pattern Ram */
|
||||
#define SK_WOL_PRAM 0x1000
|
||||
|
||||
/* Block 0x22 - 0x3f -- reserved */
|
||||
/* Block 0x22 - 0x37 -- reserved */
|
||||
|
||||
/* Block 0x38 -- Y2 PCI config registers */
|
||||
#define SK_Y2_PCI_BASE 0x1c00
|
||||
|
||||
/* Compute offset of mirrored PCI register */
|
||||
#define SK_Y2_PCI_REG(reg) ((reg) + SK_Y2_PCI_BASE)
|
||||
|
||||
/* Block 0x39 - 0x3f -- reserved */
|
||||
|
||||
/* Block 0x40 to 0x4F -- XMAC 1 registers */
|
||||
#define SK_XMAC1_BASE 0x2000
|
||||
|
|
@ -1489,6 +1502,9 @@
|
|||
#define SK_PCI_VPD_ADDR 0x0052
|
||||
#define SK_PCI_VPD_DATA 0x0054
|
||||
|
||||
#define SK_Y2_REG1_PHY1_COMA 0x10000000
|
||||
#define SK_Y2_REG1_PHY2_COMA 0x20000000
|
||||
|
||||
#define SK_PSTATE_MASK 0x0003
|
||||
#define SK_PSTATE_D0 0x0000
|
||||
#define SK_PSTATE_D1 0x0001
|
||||
|
|
@ -1541,6 +1557,11 @@ struct sk_type {
|
|||
const char *sk_name;
|
||||
};
|
||||
|
||||
#define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
|
||||
#define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32)
|
||||
|
||||
#define SK_RING_ALIGN 64
|
||||
|
||||
/* RX queue descriptor data structure */
|
||||
struct sk_rx_desc {
|
||||
u_int32_t sk_ctl;
|
||||
|
|
@ -1600,7 +1621,7 @@ struct sk_tx_desc {
|
|||
#define SK_TXSTAT \
|
||||
(SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
|
||||
|
||||
#define SK_RXBYTES(x) (x) & 0x0000FFFF;
|
||||
#define SK_RXBYTES(x) ((x) & 0x0000FFFF);
|
||||
#define SK_TXBYTES SK_RXBYTES
|
||||
|
||||
#define SK_TX_RING_CNT 512
|
||||
|
|
@ -1641,6 +1662,14 @@ struct msk_status_desc {
|
|||
#define SK_Y2_STOPC_TXSTAT 0x68
|
||||
#define SK_Y2_STOPC_OWN 0x80
|
||||
|
||||
#define SK_Y2_ST_TXA1_MSKL 0x00000fff
|
||||
#define SK_Y2_ST_TXA1_SHIFT 0
|
||||
|
||||
#define SK_Y2_ST_TXA2_MSKL 0xff000000
|
||||
#define SK_Y2_ST_TXA2_SHIFTL 24
|
||||
#define SK_Y2_ST_TXA2_MSKH 0x000f
|
||||
#define SK_Y2_ST_TXA2_SHIFTH 8
|
||||
|
||||
#define MSK_TX_RING_CNT 512
|
||||
#define MSK_RX_RING_CNT 512
|
||||
#define MSK_STATUS_RING_CNT 2048
|
||||
|
|
@ -1681,7 +1710,7 @@ struct msk_status_desc {
|
|||
|
||||
#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
|
||||
#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
|
||||
#define YU_GPSR_FCTL_TX 0x2000 /* flow control */
|
||||
#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
|
||||
#define YU_GPSR_LINK 0x1000 /* link status (down/up) */
|
||||
#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
|
||||
#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
|
||||
|
|
@ -1690,25 +1719,26 @@ struct msk_status_desc {
|
|||
#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
|
||||
#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */
|
||||
#define YU_GPSR_PARTITION 0x0008 /* partition mode */
|
||||
#define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */
|
||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */
|
||||
#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */
|
||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */
|
||||
|
||||
/* General Purpose Control Register (GPCR) */
|
||||
#define YUKON_GPCR 0x0004
|
||||
|
||||
#define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */
|
||||
#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */
|
||||
#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */
|
||||
#define YU_GPCR_RXEN 0x0800 /* Receive Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* Loopback Enable */
|
||||
#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */
|
||||
#define YU_GPCR_PAR 0x0100 /* Partition Enable */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */
|
||||
#define YU_GPCR_FLP 0x0040 /* Force Link Pass */
|
||||
#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */
|
||||
#define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed */
|
||||
#define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */
|
||||
#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */
|
||||
#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */
|
||||
|
||||
/* Transmit Control Register (TCR) */
|
||||
#define YUKON_TCR 0x0008
|
||||
|
|
@ -1847,6 +1877,24 @@ struct msk_status_desc {
|
|||
|
||||
#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT)
|
||||
|
||||
/* Receive status */
|
||||
#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */
|
||||
#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */
|
||||
#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */
|
||||
#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */
|
||||
#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */
|
||||
#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */
|
||||
#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */
|
||||
#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */
|
||||
#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */
|
||||
#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */
|
||||
#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */
|
||||
#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */
|
||||
#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */
|
||||
#define YU_RXSTAT_LENSHIFT 16
|
||||
|
||||
#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT)
|
||||
|
||||
/*
|
||||
* Registers and data structures for the XaQti Corporation XMAC II
|
||||
* Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com.
|
||||
|
|
@ -2132,6 +2180,9 @@ struct msk_status_desc {
|
|||
#define XM_RXSTAT_VLAN_LEV1 0x00010000
|
||||
#define XM_RXSTAT_VLAN_LEV2 0x00020000
|
||||
#define XM_RXSTAT_LEN 0xFFFC0000
|
||||
#define XM_RXSTAT_LENSHIFT 18
|
||||
|
||||
#define XM_RXSTAT_BYTES(x) ((x) >> XM_RXSTAT_LENSHIFT)
|
||||
|
||||
/*
|
||||
* XMAC PHY registers, indirectly accessed through
|
||||
|
|
|
|||
Loading…
Reference in New Issue