Add the appropriate memory barrier before the lock is cleared in
__sync_lock_release_{1,2,4,8}. That is, all reads and write for in inner shareability domain before the lock clear store.
This commit is contained in:
parent
27d3824d91
commit
85e6432cbe
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: atomic_swap.S,v 1.16 2021/04/24 20:34:34 skrll Exp $ */
|
||||
/* $NetBSD: atomic_swap.S,v 1.17 2021/04/26 21:40:21 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007,2012 The NetBSD Foundation, Inc.
|
||||
|
@ -88,7 +88,7 @@ STRONG_ALIAS(_atomic_swap_ptr,_atomic_swap_32)
|
|||
ENTRY_NP(__sync_lock_release_4)
|
||||
mov r1, #0
|
||||
#ifdef _ARM_ARCH_7
|
||||
dmb
|
||||
dmb ishst
|
||||
#else
|
||||
mcr p15, 0, r1, c7, c10, 5 /* data memory barrier */
|
||||
#endif
|
||||
|
@ -129,7 +129,7 @@ STRONG_ALIAS(_atomic_swap_uchar,_atomic_swap_8)
|
|||
ENTRY_NP(__sync_lock_release_1)
|
||||
mov r1, #0
|
||||
#ifdef _ARM_ARCH_7
|
||||
dmb
|
||||
dmb ishst
|
||||
#else
|
||||
mcr p15, 0, r1, c7, c10, 5 /* data memory barrier */
|
||||
#endif
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: atomic_swap_16.S,v 1.4 2015/05/17 20:57:11 justin Exp $ */
|
||||
/* $NetBSD: atomic_swap_16.S,v 1.5 2021/04/26 21:40:21 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2013 The NetBSD Foundation, Inc.
|
||||
|
@ -58,6 +58,11 @@ STRONG_ALIAS(_atomic_swap_ushort,_atomic_swap_16)
|
|||
#if (!defined(_KERNEL) || !defined(_RUMPKERNEL)) && !defined(_STANDALONE)
|
||||
ENTRY_NP(__sync_lock_release_2)
|
||||
mov r1, #0
|
||||
#ifdef _ARM_ARCH_7
|
||||
dmb ishst
|
||||
#else
|
||||
mcr p15, 0, r1, c7, c10, 5 /* data memory barrier */
|
||||
#endif
|
||||
strh r1, [r0]
|
||||
RET
|
||||
END(__sync_lock_release_2)
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: atomic_swap_64.S,v 1.11 2021/04/24 20:34:34 skrll Exp $ */
|
||||
/* $NetBSD: atomic_swap_64.S,v 1.12 2021/04/26 21:40:21 skrll Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2012 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
|
@ -57,6 +57,11 @@ CRT_ALIAS(__atomic_exchange_8,_atomic_swap_64)
|
|||
ENTRY_NP(__sync_lock_release_8)
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
#ifdef _ARM_ARCH_7
|
||||
dmb ishst
|
||||
#else
|
||||
mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
|
||||
#endif
|
||||
strd r2, r3, [r0]
|
||||
RET
|
||||
END(__sync_lock_release_8)
|
||||
|
|
Loading…
Reference in New Issue