Enable alignment faults on arm32 for both kernel and userland.
If COMPAT_15 and EXEC_AOUT are defined, support per-process alignment checking where AFLTs are always enabled when running kernel code and userland ELF binaries, and dynamically disabled/ enabled when switching to/from a.out binaries. This is necessary in order to execute older a.out binaries, where gcc made deliberate use of misaligned loads under certain circumstances.
This commit is contained in:
scw
parent
987510aee5
commit
84c17a8163
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@ -1,4 +1,4 @@
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/* $NetBSD: arm_machdep.c,v 1.6 2003/01/17 22:28:48 thorpej Exp $ */
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/* $NetBSD: arm_machdep.c,v 1.7 2003/10/25 19:44:42 scw Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -72,10 +72,11 @@
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*/
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.6 2003/01/17 22:28:48 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.7 2003/10/25 19:44:42 scw Exp $");
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#include <sys/exec.h>
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#include <sys/proc.h>
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@ -133,6 +134,11 @@ setregs(struct lwp *l, struct exec_package *pack, u_long stack)
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tf->tf_spsr = PSR_USR32_MODE;
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#endif
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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if (pack->ep_es->es_check == exec_aout_makecmds)
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l->l_addr->u_pcb.pcb_flags = PCB_NOALIGNFLT;
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else
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#endif
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l->l_addr->u_pcb.pcb_flags = 0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.63 2003/09/06 09:31:37 rearnsha Exp $ */
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/* $NetBSD: cpufunc.c,v 1.64 2003/10/25 19:44:42 scw Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -46,7 +46,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.63 2003/09/06 09:31:37 rearnsha Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.64 2003/10/25 19:44:42 scw Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_cpuoptions.h"
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@ -1614,7 +1614,8 @@ arm6_setup(args)
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/* Set up default control registers bits */
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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| CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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@ -1662,7 +1663,8 @@ arm7_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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| CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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@ -1750,7 +1752,8 @@ arm8_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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| CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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@ -1830,7 +1833,7 @@ arm9_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE;
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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@ -1876,7 +1879,8 @@ arm10_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE;
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE
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| CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
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@ -1931,7 +1935,7 @@ sa110_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE;
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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@ -1988,7 +1992,8 @@ sa11x0_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
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| CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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@ -2036,7 +2041,7 @@ ixp12x0_setup(args)
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE;
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE
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| CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE
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@ -2097,7 +2102,7 @@ xscale_setup(args)
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
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| CPU_CONTROL_BPRD_ENABLE;
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| CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_AFLT_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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@ -1,4 +1,4 @@
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/* $NetBSD: exception.S,v 1.8 2003/01/06 13:05:00 wiz Exp $ */
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/* $NetBSD: exception.S,v 1.9 2003/10/25 19:44:42 scw Exp $ */
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/*
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* Copyright (c) 1994-1997 Mark Brinicombe.
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@ -46,6 +46,9 @@
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*/
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#include "opt_ipkdb.h"
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include "opt_multiprocessor.h"
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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@ -54,8 +57,45 @@
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.text
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.align 0
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Lastpending:
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.word _C_LABEL(astpending)
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.Lastpending:
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.word _C_LABEL(astpending)
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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#ifndef MULTIPROCESSOR
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.Lcurpcb:
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.word _C_LABEL(curpcb)
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.Lcpu_info_store:
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.word _C_LABEL(cpu_info_store)
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#define GET_CURPCB \
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ldr r1, .Lcurpcb ;\
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ldr r1, [r1]
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#define GET_CPUINFO \
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ldr r0, .Lcpu_info_store
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#else
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.Lcpu_info:
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.word _C_LABEL(cpu_info)
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#define GET_CURPCB \
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ldr r4, .Lcpu_info ;\
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bl _C_LABEL(cpu_number) ;\
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ldr r0, [r4, r0, lsl #2] ;\
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ldr r1, [r0, #CI_CURPCB]
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#define GET_CPUINFO /* nothing to do */
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#endif
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#define ENABLE_ALIGNMENT_FAULTS \
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GET_CURPCB ;\
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ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
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tst r1, #PCB_NOALIGNFLT ;\
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beq 1f /* Alignment faults already enabled */ ;\
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GET_CPUINFO ;\
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ldr r2, .Lcpufuncs ;\
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ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\
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mov r0, #-1 ;\
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mov lr, pc ;\
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ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
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1:
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#endif /* COMPAT_15 && EXEC_AOUT */
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/*
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* General exception exit handler
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@ -77,7 +117,11 @@ exception_exit:
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teq r0, #(PSR_USR32_MODE)
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bne .Ldo_exit /* Not USR mode so no AST delivery */
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ldr r5, Lastpending /* Get address of astpending */
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ldr r5, .Lastpending /* Get address of astpending */
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#if defined(COMPAT_15) && defined(EXEC_AOUT) && !defined(MULTIPROCESSOR)
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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#endif
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Lexception_exit_loop:
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orr r0, r4, #(I32_bit) /* Block IRQs */
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@ -87,6 +131,28 @@ Lexception_exit_loop:
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teq r1, #0x00000000
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bne .Ldo_ast
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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/* Disable alignment faults for the process, if necessary. */
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r1, [r6]
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#endif
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ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
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tst r1, #PCB_NOALIGNFLT
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beq 1f /* Keep alignment faults enabled */
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ldr r1, [r7, #CI_CTRL] /* Fetch control register */
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ldr r2, .Lcpufuncs
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mov r0, #-1
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
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mov lr, pc
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ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
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1:
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#endif
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PULLFRAMEFROMSVCANDEXIT /* No AST so exit */
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.Ldo_ast:
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@ -127,12 +193,20 @@ Lreset_panicmsg:
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ASENTRY_NP(swi_entry)
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PUSHFRAME
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp /* Pass the frame to any function */
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bl _C_LABEL(swi_handler) /* It's a SWI ! */
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ldr r5, Lastpending /* Get address of astpending */
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ldr r5, .Lastpending /* Get address of astpending */
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mrs r4, cpsr /* Get CPSR */
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#if defined(COMPAT_15) && defined(EXEC_AOUT) && !defined(MULTIPROCESSOR)
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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#endif
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.Lswi_exit_loop:
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orr r0, r4, #(I32_bit) /* Disable IRQs */
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@ -142,6 +216,27 @@ ASENTRY_NP(swi_entry)
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teq r1, #0x00000000
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bne .Ldo_swi_ast
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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/* Disable alignment faults for the process, if necessary. */
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r1, [r6]
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#endif
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ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
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tst r1, #PCB_NOALIGNFLT
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beq 1f /* Keep alignment faults enabled */
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ldr r1, [r7, #CI_CTRL] /* Fetch control register */
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ldr r2, .Lcpufuncs
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mov r0, #-1
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
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mov lr, pc
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ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
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1:
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#endif
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PULLFRAME
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movs pc, lr /* Exit */
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@ -165,6 +260,10 @@ ASENTRY_NP(prefetch_abort_entry)
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PUSHFRAMEINSVC
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp /* pass the stack pointer as r0 */
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adr lr, exception_exit
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@ -200,6 +299,10 @@ ASENTRY_NP(data_abort_entry)
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PUSHFRAMEINSVC /* Push trap frame and switch */
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/* to SVC32 mode */
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp /* pass the stack pointer as r0 */
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adr lr, exception_exit
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@ -307,10 +410,37 @@ ASENTRY_NP(undefined_entry)
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* Now to IPKDB.
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*/
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.Lgoipkdb:
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp
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bl _C_LABEL(ipkdb_trap_glue)
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ldr r1, .Lipkdb_trap_return
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str r0,[r1]
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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ldr r1, [r6]
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#endif
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ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
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tst r1, #PCB_NOALIGNFLT
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beq 1f /* Keep alignment faults enabled */
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ldr r1, [r7, #CI_CTRL] /* Fetch control register */
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ldr r2, .Lcpufuncs
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mov r0, #-1
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
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mov lr, pc
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ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
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1:
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#endif
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/*
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* Have to load all registers from the stack.
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*
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@ -392,6 +522,9 @@ Lundefined_handler_indirection:
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ENTRY_NP(undefinedinstruction_bounce)
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PUSHFRAMEINSVC
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp
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bl _C_LABEL(undefinedinstruction)
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@ -1,4 +1,4 @@
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/* $NetBSD: fault.c,v 1.37 2003/10/15 14:07:03 scw Exp $ */
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/* $NetBSD: fault.c,v 1.38 2003/10/25 19:44:42 scw Exp $ */
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/*
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* Copyright 2003 Wasabi Systems, Inc.
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@ -82,7 +82,7 @@
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#include "opt_pmap_debug.h"
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#include <sys/types.h>
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__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.37 2003/10/15 14:07:03 scw Exp $");
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__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.38 2003/10/25 19:44:42 scw Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -240,14 +240,18 @@ badaddr_read(void *addr, size_t size, void *rptr)
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#define TRAP_CODE ((fault_status & 0x0f) | (fault_address & 0xfffffff0))
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/* Determine if 'x' is an alignment fault */
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#define IS_ALIGN_FAULT(x) \
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(((1 << (x)) & \
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((1 << FAULT_ALIGN_0) | (1 << FAULT_ALIGN_1))) != 0)
|
||||
|
||||
/* Determine if we can recover from a fault */
|
||||
#define IS_FATAL_FAULT(x) \
|
||||
(((1 << (x)) & \
|
||||
((1 << FAULT_WRTBUF_0) | (1 << FAULT_WRTBUF_1) | \
|
||||
(1 << FAULT_BUSERR_0) | (1 << FAULT_BUSERR_1) | \
|
||||
(1 << FAULT_BUSERR_2) | (1 << FAULT_BUSERR_3) | \
|
||||
(1 << FAULT_BUSTRNL1) | (1 << FAULT_BUSTRNL2) | \
|
||||
(1 << FAULT_ALIGN_0) | (1 << FAULT_ALIGN_1))) != 0)
|
||||
(1 << FAULT_BUSTRNL1) | (1 << FAULT_BUSTRNL2))) != 0)
|
||||
|
||||
void
|
||||
data_abort_handler(frame)
|
||||
|
|
@ -400,6 +404,26 @@ copyfault:
|
|||
};
|
||||
|
||||
/* Now act on the fault type */
|
||||
if (IS_ALIGN_FAULT(fault_code)) {
|
||||
if (user) {
|
||||
KSI_INIT_TRAP(&ksi);
|
||||
ksi.ksi_signo = SIGBUS;
|
||||
ksi.ksi_code = BUS_ADRALN;
|
||||
ksi.ksi_addr = (u_int32_t *)fault_address;
|
||||
ksi.ksi_trap = TRAP_CODE;
|
||||
ksi.ksi_errno = error;
|
||||
goto trapsignal;
|
||||
}
|
||||
#if defined(DDB) || defined(KGDB)
|
||||
printf("Alignment fault in kernel (frame = %p)\n", frame);
|
||||
report_abort(NULL, fault_status, fault_address, fault_pc);
|
||||
kdb_trap(T_FAULT, frame);
|
||||
return;
|
||||
#else
|
||||
panic("Alignment fault in kernel - we're dead");
|
||||
#endif
|
||||
}
|
||||
|
||||
if (fatal_fault) {
|
||||
/*
|
||||
* None of these faults should happen on a perfectly
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: genassym.cf,v 1.25 2003/09/11 18:54:33 scw Exp $
|
||||
# $NetBSD: genassym.cf,v 1.26 2003/10/25 19:44:42 scw Exp $
|
||||
|
||||
# Copyright (c) 1982, 1990 The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
|
|
@ -57,6 +57,8 @@ include <machine/frame.h>
|
|||
include <machine/vmparam.h>
|
||||
|
||||
include "opt_multiprocessor.h"
|
||||
include "opt_compat_netbsd.h"
|
||||
include "opt_execfmt.h"
|
||||
|
||||
define __PROG32 1
|
||||
ifdef __ARM_FIQ_INDIRECT
|
||||
|
|
@ -108,6 +110,7 @@ define PCB_LR offsetof(struct pcb, pcb_un.un_32.pcb32_lr)
|
|||
define PCB_PC offsetof(struct pcb, pcb_un.un_32.pcb32_pc)
|
||||
define PCB_UND_SP offsetof(struct pcb, pcb_un.un_32.pcb32_und_sp)
|
||||
define PCB_ONFAULT offsetof(struct pcb, pcb_onfault)
|
||||
define PCB_NOALIGNFLT PCB_NOALIGNFLT
|
||||
|
||||
define USER_SIZE sizeof(struct user)
|
||||
|
||||
|
|
@ -147,12 +150,16 @@ define CF_DCACHE_WB_RANGE offsetof(struct cpu_functions, cf_dcache_wb_range)
|
|||
define CF_TLB_FLUSHID_SE offsetof(struct cpu_functions, cf_tlb_flushID_SE)
|
||||
define CF_CONTEXT_SWITCH offsetof(struct cpu_functions, cf_context_switch)
|
||||
define CF_SLEEP offsetof(struct cpu_functions, cf_sleep)
|
||||
define CF_CONTROL offsetof(struct cpu_functions, cf_control)
|
||||
|
||||
define CI_CURPRIORITY offsetof(struct cpu_info, ci_schedstate.spc_curpriority)
|
||||
ifdef MULTIPROCESSOR
|
||||
define CI_CURLWP offsetof(struct cpu_info, ci_curlwp)
|
||||
define CI_CURPCB offsetof(struct cpu_info, ci_curpcb)
|
||||
endif
|
||||
if defined(COMPAT_15) && defined(EXEC_AOUT)
|
||||
define CI_CTRL offsetof(struct cpu_info, ci_ctrl)
|
||||
endif
|
||||
|
||||
# Constants required for in_cksum() and friends.
|
||||
define M_LEN offsetof(struct mbuf, m_len)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pcb.h,v 1.10 2003/10/13 21:46:39 scw Exp $ */
|
||||
/* $NetBSD: pcb.h,v 1.11 2003/10/25 19:44:42 scw Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Matt Thomas <matt@3am-software.com>.
|
||||
|
|
@ -82,6 +82,7 @@ struct pcb_arm26 {
|
|||
struct pcb {
|
||||
u_int pcb_flags;
|
||||
#define PCB_OWNFPU 0x00000001
|
||||
#define PCB_NOALIGNFLT 0x00000002 /* For COMPAT_15/EXEC_AOUT */
|
||||
struct trapframe *pcb_tf;
|
||||
caddr_t pcb_onfault; /* On fault handler */
|
||||
union {
|
||||
|
|
|
|||
Loading…
Reference in New Issue