HD64461 video module.
This commit is contained in:
uch
parent
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commit
842b6023c3
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC,v 1.2 2001/04/23 11:22:19 uch Exp $
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# $NetBSD: GENERIC,v 1.3 2001/06/04 17:08:36 uch Exp $
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#
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# GENERIC kernel for SH3+HD64461 based machines.
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#
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@ -18,12 +18,8 @@ options KTRACE # system call tracing support
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options MSGBUFSIZE=65534
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# Standard system options
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options RTC_OFFSET=-540 # hardware clock is this many mins. west of GMT
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# Compatibility options
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options COMPAT_43
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options SCSIVERBOSE # human readable SCSI error messages
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options PCMCIAVERBOSE # verbose PCMCIA configuration messages
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@ -72,9 +68,7 @@ shb1 at mainbus? id HITACHI
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#
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# Workstation Console attachments
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#
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bivideo* at mainbus? id HP
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hpcfb* at bivideo?
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hpcfb* at hd64461video?
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wsdisplay* at hpcfb?
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pfckbd* at mainbus? id HP
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hpckbd* at pfckbd?
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@ -90,6 +84,7 @@ scif0 at shb0 port 0xa4000008 irq 12
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hd64461if0 at shb0 irq 4
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hd64461pcmcia* at hd64461if0
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hd64461video* at hd64461if0
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#
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# HITACHI PERSONA
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@ -108,15 +103,15 @@ pcmcia1 at hd64461pcmcia? controller 1 socket ? # memory card only
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ne* at pcmcia0 function ? # NE2000-compatible Ethernet
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ep* at pcmcia0 function ? # 3Com 3c589 and 3c562 Ethernet
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mbe* at pcmcia0 function ? # MB8696x based Ethernet
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#wi* at pcmcia0 function ? # Lucent WaveLan IEEE (802.11)
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#mhzc* at pcmcia0 function ? # Megahertz Ethernet/Modem combo cards
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#com* at mhzc?
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#sm* at mhzc?
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wi* at pcmcia0 function ? # Lucent WaveLan IEEE (802.11)
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mhzc* at pcmcia0 function ? # Megahertz Ethernet/Modem combo cards
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com* at mhzc?
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sm* at mhzc?
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# PCMCIA SCSI interfaces
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#aic* at pcmcia0 function ? # Adaptec APA-1460 SCSI
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aic* at pcmcia0 function ? # Adaptec APA-1460 SCSI
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#scsibus* at aic?
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scsibus* at aic?
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# PCMCIA IDE disk
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# PC-Card slot
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@ -127,7 +122,7 @@ wdc0 at pcmcia1 function ?
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wd* at wdc0 channel ? drive ? flags 0x0000
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# SCSI devices
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#sd* at scsibus? target ? lun ? # SCSI disk drives
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sd* at scsibus? target ? lun ? # SCSI disk drives
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# Network Interfaces
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@ -1,4 +1,4 @@
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# $NetBSD: files.hpcsh,v 1.11 2001/04/23 11:22:19 uch Exp $
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# $NetBSD: files.hpcsh,v 1.12 2001/06/04 17:08:36 uch Exp $
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#
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maxpartitions 8
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@ -72,6 +72,11 @@ file arch/hpcsh/dev/hd64461/hd64461pcmcia.c hd64461pcmcia
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attach com at hd64461if with hd64461uart
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file arch/hpcsh/dev/hd64461/hd64461uart.c hd64461uart
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device hd64461video: hpcfbif
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attach hd64461video at hd64461if
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file arch/hpcsh/dev/hd64461/hd64461video.c hd64461video
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file dev/hpc/video_subr.c hd64461video
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# network devices MII bus
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include "dev/mii/files.mii"
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@ -1,4 +1,4 @@
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/* $NetBSD: hd64461reg.h,v 1.1 2001/02/21 15:39:09 uch Exp $ */
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/* $NetBSD: hd64461reg.h,v 1.2 2001/06/04 17:08:36 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -47,6 +47,7 @@
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#define HD64461_REGSIZE 0x02000000
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#define HD64461_FBBASE (SH3_AREA4_BASE + 0x02000000)
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#define HD64461_FBSIZE 0x02000000
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#define HD64461_FBPAGESIZE 0x1000
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/* SH3 Area 5 (PCC1 memory space) */
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#define HD64461_PCC1_MEMBASE SH3_AREA5_BASE
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,404 @@
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/* $NetBSD: hd64461videoreg.h,v 1.1 2001/06/04 17:08:36 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* LCD Controller Control Register
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*/
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/* Base Address Register */
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#define HD64461_LCDCBAR_REG16 0xb0001000
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#define HD64461_LCDCBAR_MASK 0x3fff
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#define HD64461_LCDCBAR_SHIFT 12
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#define HD64461_LCDCBAR_BASEADDR(x) \
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(((x) & HD64461_LCDCBAR_MASK) << HD64461_LCDCBAR_SHIFT)
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/* Line Address Offset Register */
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#define HD64461_LCDCLOR_REG16 0xb0001002
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#define HD64461_LCDCLOR_MASK 0x07ff
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#define HD64461_LCDCLOR(x) ((x) & HD64461_LCDCLOR_MASK)
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/* LCDC Control Register */
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#define HD64461_LCDCCR_REG16 0xb0001004
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#define HD64461_LCDCCR_STBAK 0x0400
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#define HD64461_LCDCCR_STREQ 0x0100
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#define HD64461_LCDCCR_MOFF 0x0080
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#define HD64461_LCDCCR_REFSEL 0x0040
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#define HD64461_LCDCCR_EPON 0x0020
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#define HD64461_LCDCCR_SPON 0x0010
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#define HD64461_LCDCCR_DSPSEL_MASK 0x7
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#define HD64461_LCDCCR_DSPSEL(x) ((x) & HD64461_LCDCCR_DSPSEL_MASK)
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#define HD64461_LCDCCR_DSPSEL_LCD_CRT 0x4
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#define HD64461_LCDCCR_DSPSEL_CRT 0x2
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#define HD64461_LCDCCR_DSPSEL_LCD 0x1
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/* LCD Display Register */
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/* 1 */
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#define HD64461_LCDLDR1_REG16 0xb0001010
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#define HD64461_LCDLDR1_DINV 0x0100
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#define HD64461_LCDLDR1_DON 0x0001
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/* 2 */
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#define HD64461_LCDLDR2_REG16 0xb0001012
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#define HD64461_LCDLDR2_CC1 0x0080
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#define HD64461_LCDLDR2_CC2 0x0040
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#define HD64461_LCDLDR2_LM_MASK 0x7
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#define HD64461_LCDLDR2_LM(x) ((x) & HD64461_LCDLDR2_LM_MASK)
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#define HD64461_LCDLDR2_LM_COLOR 0x4
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#define HD64461_LCDLDR2_LM_GRAY8 0x1
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#define HD64461_LCDLDR2_LM_GRAY4 0x0
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/* 3 */
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#define HD64461_LCDLDR3_REG16 0xb000101e
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#define HD64461_LCDLDR3_CS_SHIFT 5
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#define HD64461_LCDLDR3_CS_MASK 0x1f
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#define HD64461_LCDLDR3_CS(cr) \
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(((cr) >> HD64461_LCDLDR3_CS_SHIFT) & \
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HD64461_LCDLDR3_CS_MASK)
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#define HD64461_LCDLDR3_CS_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDR3_CS_SHIFT) & \
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(HD64461_LCDLDR3_CS_MASK << HD64461_LCDLDR3_CS_SHIFT)))
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#define HD64461_LCDLDR3_CG_MASK 0xf
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#define HD64461_LCDLDR3_CG(cr) \
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((cr) & HD64461_LCDLDR3_CG_MASK)
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#define HD64461_LCDLDR3_CG_CLR(cr) \
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((cr) & ~HD64461_LCDLDR3_CG_MASK)
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#define HD64461_LCDLDR3_CG_SET(cr, val) \
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((cr) | ((val) & HD64461_LCDLDR3_CG_MASK))
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/*
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* select CL2 frequency
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* 0x0 15 MHz (color) 15/2 (monochrome)
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* 0x1 2.5 MHz
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* 0x2 3.75 Mhz
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* 0x4 5 Mhz
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* 0x8 7.5 Mhz
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* 0x10 10 Mhz
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*/
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#define HD64461_LCDLDR3_CG_COLOR16 0x8
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#define HD64461_LCDLDR3_CG_COLOR8 0x4
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#define HD64461_LCDLDR3_CG_GRAY6 0x3
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#define HD64461_LCDLDR3_CG_GRAY4 0x2
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#define HD64461_LCDLDR3_CG_GRAY2 0x1
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#define HD64461_LCDLDR3_CG_GRAY1 0x0
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/* LCD Number of Characters in Horizontal Register */
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#define HD64461_LCDLDHNCR_REG16 0xb0001014
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#define HD64461_LCDLDHNCR_NHD_SHIFT 8
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#define HD64461_LCDLDHNCR_NHD_MASK 0xff
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#define HD64461_LCDLDHNCR_NHD(cr) \
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(((cr) >> HD64461_LCDLDHNCR_NHD_SHIFT) & \
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HD64461_LCDLDHNCR_NHD_MASK)
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#define HD64461_LCDLDHNCR_NHD_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDHNCR_NHD_SHIFT) & \
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(HD64461_LCDLDHNCR_NHD_MASK << HD64461_LCDLDHNCR_NHD_SHIFT)))
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#define HD64461_LCDLDHNCR_NHT_SHIFT 0
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#define HD64461_LCDLDHNCR_NHT_MASK 0xff
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#define HD64461_LCDLDHNCR_NHT(cr) \
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(((cr) >> HD64461_LCDLDHNCR_NHT_SHIFT) & \
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HD64461_LCDLDHNCR_NHT_MASK)
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#define HD64461_LCDLDHNCR_NHT_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDHNCR_NHT_SHIFT) & \
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(HD64461_LCDLDHNCR_NHT_MASK << HD64461_LCDLDHNCR_NHT_SHIFT)))
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/* Start Position of Horizontal Register */
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#define HD64461_LCDLDHNSR_REG16 0xb0001016
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#define HD64461_LCDLDHNSR_HSW_SHIFT 8
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#define HD64461_LCDLDHNSR_HSW_MASK 0xf
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#define HD64461_LCDLDHNSR_HSW(cr) \
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(((cr) >> HD64461_LCDLDHNSR_HSW_SHIFT) & \
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HD64461_LCDLDHNSR_HSW_MASK)
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#define HD64461_LCDLDHNSR_HSW_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDHNSR_HSW_SHIFT) & \
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(HD64461_LCDLDHNSR_HSW_MASK << HD64461_LCDLDHNSR_HSW_SHIFT)))
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#define HD64461_LCDLDHNSR_HSP_SHIFT 0
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#define HD64461_LCDLDHNSR_HSP_MASK 0xff
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#define HD64461_LCDLDHNSR_HSP(cr) \
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(((cr) >> HD64461_LCDLDHNSR_HSP_SHIFT) & \
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HD64461_LCDLDHNSR_HSP_MASK)
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#define HD64461_LCDLDHNSR_HSP_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDHNSR_HSP_SHIFT) & \
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(HD64461_LCDLDHNSR_HSP_MASK << HD64461_LCDLDHNSR_HSP_SHIFT)))
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/* Total Vertical Lines Register */
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#define HD64461_LCDLDVNTR_REG16 0xb0001018
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#define HD64461_LCDLDVNTR_VTL_SHIFT 0
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#define HD64461_LCDLDVNTR_VTL_MASK 0x3ff
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#define HD64461_LCDLDVNTR_VTL(cr) \
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(((cr) >> HD64461_LCDLDVNTR_VTL_SHIFT) & \
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HD64461_LCDLDVNTR_VTL_MASK)
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#define HD64461_LCDLDVNTR_VTL_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDVNTR_VTL_SHIFT) & \
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(HD64461_LCDLDVNTR_VTL_MASK << HD64461_LCDLDVNTR_VTL_SHIFT)))
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/* Display Vertical Lines Register */
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#define HD64461_LCDLDVNDR_REG16 0xb000101a
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#define HD64461_LCDLDVNDR_VDL_SHIFT 0
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#define HD64461_LCDLDVNDR_VDL_MASK 0x3ff
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#define HD64461_LCDLDVNDR_VDL(cr) \
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(((cr) >> HD64461_LCDLDVNDR_VDL_SHIFT) & \
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HD64461_LCDLDVNDR_VDL_MASK)
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#define HD64461_LCDLDVNDR_VDL_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDLDVNDR_VDL_SHIFT) & \
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(HD64461_LCDLDVNDR_VDL_MASK << HD64461_LCDLDVNDR_VDL_SHIFT)))
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/* Vertical Synchronization Position Register */
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#define HD64461_LCDLDVSPR_REG16 0xb000101c
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#define HD64461_LCDLDVSPR_VSP_SHIFT 0
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#define HD64461_LCDLDVSPR_VSP_MASK 0x3ff
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#define HD64461_LCDLDVSPR_VSP(cr) \
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((cr) & HD64461_LCDLDVSPR_VSP_MASK)
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#define HD64461_LCDLDVSPR_VSP_SET(cr, val) \
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((cr) | ((val) & HD64461_LCDLDVSPR_VSP_MASK))
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/*
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* CRT Control Register
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*/
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/* CRTC Total Vertical Lines Register */
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#define HD64461_LCDCRTVTR_REG16 0xb0001020
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#define HD64461_LCDCRTVTR_SHIFT 0
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#define HD64461_LCDCRTVTR_MASK 0x3ff
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#define HD64461_LCDCRTVTR(cr) \
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(((cr) >> HD64461_LCDCRTVTR_SHIFT) & \
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HD64461_LCDCRTVTR_MASK)
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#define HD64461_LCDCRTVTR_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDCRTVTR_SHIFT) & \
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(HD64461_LCDCRTVTR_MASK << HD64461_LCDCRTVTR_SHIFT)))
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/* CRTC Vertical Retrace Start Register */
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#define HD64461_LCDCRTVRSR_REG16 0xb0001022
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#define HD64461_LCDCRTVRSR_SHIFT 0
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#define HD64461_LCDCRTVRSR_MASK 0x3ff
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#define HD64461_LCDCRTVRSR(cr) \
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(((cr) >> HD64461_LCDCRTVRSR_SHIFT) & \
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HD64461_LCDCRTVRSR_MASK)
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#define HD64461_LCDCRTVRSR_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDCRTVRSR_SHIFT) & \
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(HD64461_LCDCRTVRSR_MASK << HD64461_LCDCRTVRSR_SHIFT)))
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/* CRTC Vertical Retrace End Register */
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#define HD64461_LCDCRTVRER_REG16 0xb0001024
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#define HD64461_LCDCRTVRER_SHIFT 0
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#define HD64461_LCDCRTVRER_MASK 0xf
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#define HD64461_LCDCRTVRER(cr) \
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(((cr) >> HD64461_LCDCRTVRER_SHIFT) & HD64461_LCDCRTVRER_MASK)
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#define HD64461_LCDCRTVRER_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDCRTVRER_SHIFT) & \
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(HD64461_LCDCRTVRER_MASK << HD64461_LCDCRTVRER_SHIFT)))
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/*
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* Palette Register
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*/
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/* Color Palette Write Address Register */
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#define HD64461_LCDCPTWAR_REG16 0xb0001030
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#define HD64461_LCDCPTWAR_SHIFT 8
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#define HD64461_LCDCPTWAR_MASK 0xff
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#define HD64461_LCDCPTWAR_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDCPTWAR_SHIFT) & \
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(HD64461_LCDCPTWAR_MASK << HD64461_LCDCPTWAR_SHIFT)))
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/* Color Palette Write Data Register */
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#define HD64461_LCDCPTWDR_REG16 0xb0001032
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#define HD64461_LCDCPTWDR_SHIFT 0
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#define HD64461_LCDCPTWDR_MASK 0x3f
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#define HD64461_LCDCPTWDR_SET(cr, val) \
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((cr) | ((val) & HD64461_LCDCPTWDR_MASK))
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/* Color Palette READ Address Register */
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#define HD64461_LCDCPTRAR_REG16 0xb0001034
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#define HD64461_LCDCPTRAR_SHIFT 8
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#define HD64461_LCDCPTRAR_MASK 0xff
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#define HD64461_LCDCPTRAR_SET(cr, val) \
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((cr) | (((val) << HD64461_LCDCPTRAR_SHIFT) & \
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(HD64461_LCDCPTRAR_MASK << HD64461_LCDCPTRAR_SHIFT)))
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/* Color Palette READ Data Register */
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#define HD64461_LCDCPTRDR_REG16 0xb0001036
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#define HD64461_LCDCPTRDR_SHIFT 0
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#define HD64461_LCDCPTRDR_MASK 0x3f
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#define HD64461_LCDCPTRDR(cr) ((cr) & HD64461_LCDCPTRDR_MASK)
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/*
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* Acceleration Common Register
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*/
|
||||
/* Display Resolution Offset Register */
|
||||
#define HD64461_LCDGRDOR_REG16 0xb0001040
|
||||
#define HD64461_LCDGRDOR_SHIFT 0
|
||||
#define HD64461_LCDGRDOR_MASK 0x7ff
|
||||
#define HD64461_LCDGRDOR(cr) \
|
||||
(((cr) >> HD64461_LCDGRDOR_SHIFT) & \
|
||||
HD64461_LCDGRDOR_MASK)
|
||||
#define HD64461_LCDGRDOR_SET(cr, val) \
|
||||
((cr) | (((val) << HD64461_LCDGRDOR_SHIFT) & \
|
||||
(HD64461_LCDGRDOR_MASK << HD64461_LCDGRDOR_SHIFT)))
|
||||
|
||||
/* Solid Color Register */
|
||||
#define HD64461_LCDGRSCR_REG16 0xb0001042
|
||||
|
||||
/* Accelerator Configuration Register */
|
||||
#define HD64461_LCDGRCFGR_REG16 0xb0001044
|
||||
#define HD64461_LCDGRCFGR_ACCSTATUS 0x0010
|
||||
#define HD64461_LCDGRCFGR_ACCRESET 0x0008
|
||||
#define HD64461_LCDGRCFGR_ACCSTART_MASK 0x6
|
||||
#define HD64461_LCDGRCFGR_ACCSTART_BITBLT 0x0006
|
||||
#define HD64461_LCDGRCFGR_ACCSTART_LINE 0x0004
|
||||
#define HD64461_LCDGRCFGR_ACCSTART_OFF 0x0000
|
||||
#define HD64461_LCDGRCFGR_COLORDEPTH_8BPP 0x0001
|
||||
|
||||
/*
|
||||
* Line Drawing Register
|
||||
*/
|
||||
/* Line Start Address Register */
|
||||
#define HD64461_LCDLNSARH_REG16 0xb0001046
|
||||
#define HD64461_LCDLNSARH_MASK 0x0007
|
||||
#define HD64461_LCDLNSARL_REG16 0xb0001048
|
||||
#define HD64461_LCDLNSARL_MASK 0xffff
|
||||
|
||||
/* Axis Pixel Length Register */
|
||||
#define HD64461_LCDLNAXLR_REG16 0xb000104a
|
||||
#define HD64461_LCDLNAXLR_MASK 0x07ff
|
||||
|
||||
/* Diagonal Regsiter */
|
||||
#define HD64461_LCDLNDGR_REG16 0xb000104c
|
||||
#define HD64461_LCDLNDGR_LNDGR_SIGN 0x8000
|
||||
#define HD64461_LCDLNDGR_LNDGR_MASK 0x07ff
|
||||
#define HD64461_LCDLNDGR_LNDGR_SET(cr, x) \
|
||||
((cr) | ((x) & HD64461_LCDLNDGR_LNDGR_MASK))
|
||||
|
||||
/* Axial Register */
|
||||
#define HD64461_LCDLNAXR_REG16 0xb000104e
|
||||
#define HD64461_LCDLNAXR_LNAXR_MASK 0x0fff
|
||||
#define HD64461_LCDLNAXR_LNAXR_SET(cr, x) \
|
||||
((cr) | ((x) & HD64461_LCDLNAXR_LNAXR_MASK))
|
||||
|
||||
/* Start Error Term Register */
|
||||
#define HD64461_LCDLNERTR_REG16 0xb0001050
|
||||
#define HD64461_LCDLNERTR_LNERTR_SIGN 0x8000
|
||||
#define HD64461_LCDLNERTR_LNERTR_MASK 0x07ff
|
||||
#define HD64461_LCDLNERTR_LNERTR_SET(cr, x) \
|
||||
((cr) | ((x) & HD64461_LCDLNERTR_LNERTR_MASK))
|
||||
|
||||
/* Line Mode Register */
|
||||
#define HD64461_LCDLNMDR_REG16 0xb0001052
|
||||
#define HD64461_LCDLNMDR_MASK 0x0003
|
||||
/*
|
||||
* 2 1
|
||||
* 3 0
|
||||
* 4 7
|
||||
* 5 6
|
||||
*
|
||||
* 1 or 5 ... 3
|
||||
* 2 or 6 ... 2
|
||||
* 0 or 4 ... 1
|
||||
* 3 or 7 ... 0
|
||||
*/
|
||||
|
||||
/*
|
||||
* BitBLT Register
|
||||
*/
|
||||
/* Source Start Address Register (19 bit) */
|
||||
#define HD64461_LCDBBTSSARH_REG16 0xb0001054
|
||||
#define HD64461_LCDBBTSSARH_SHIFT 16
|
||||
#define HD64461_LCDBBTSSARH_MASK 0x0007
|
||||
#define HD64461_LCDBBTSSARL_REG16 0xb0001056
|
||||
#define HD64461_LCDBBTSSARL_MASK 0xffff
|
||||
#define HD64461_LCDBBTSSARH(x) \
|
||||
(((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK)
|
||||
#define HD64461_LCDBBTSSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK)
|
||||
|
||||
/* Destination Start Address Register (19 bit) */
|
||||
#define HD64461_LCDBBTDSARH_REG16 0xb0001058
|
||||
#define HD64461_LCDBBTDSARH_SHIFT 16
|
||||
#define HD64461_LCDBBTDSARH_MASK 0x0007
|
||||
#define HD64461_LCDBBTDSARL_REG16 0xb000105a
|
||||
#define HD64461_LCDBBTDSARL_MASK 0xffff
|
||||
#define HD64461_LCDBBTDSARH(x) \
|
||||
(((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK)
|
||||
#define HD64461_LCDBBTDSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK)
|
||||
|
||||
/* Destination Block Width Register */
|
||||
#define HD64461_LCDBBTDWR_REG16 0xb000105c
|
||||
#define HD64461_LCDBBTDWR_MASK 0x07ff
|
||||
|
||||
/* Destination Block Height Register */
|
||||
#define HD64461_LCDBBTDHR_REG16 0xb000105e
|
||||
#define HD64461_LCDBBTDHR_MASK 0x07ff
|
||||
|
||||
/* Pattern Start Address Register (19 bit) */
|
||||
#define HD64461_LCDBBTPARH_REG16 0xb0001060
|
||||
#define HD64461_LCDBBTPARH_MASK 0x0007
|
||||
#define HD64461_LCDBBTPARL_REG16 0xb0001062
|
||||
|
||||
/* Mask Start Address Register (19 bit) */
|
||||
#define HD64461_LCDBBTMARH_REG16 0xb0001064
|
||||
#define HD64461_LCDBBTMARH_MASK 0x0007
|
||||
#define HD64461_LCDBBTMARL_REG16 0xb0001066
|
||||
|
||||
/* ROP Register */
|
||||
#define HD64461_LCDBBTROPR_REG16 0xb0001068
|
||||
|
||||
/* BitBLT Mode Register */
|
||||
#define HD64461_LCDBBTMDR_REG16 0xb000106a
|
||||
#define HD64461_LCDBBTMDR_MASKENABLE 0x0020
|
||||
#define HD64461_LCDBBTMDR_PATSELECT_SOLIDCOLOR 0x0010
|
||||
#define HD64461_LCDBBTMDR_SHIFT 2
|
||||
#define HD64461_LCDBBTMDR_MASK 0x3
|
||||
#define HD64461_LCDBBTMDR(cr) \
|
||||
(((cr) >> HD64461_LCDBBTMDR_SHIFT) & HD64461_LCDBBTMDR_MASK)
|
||||
|
||||
#define HD64461_LCDBBTMDR_SET(cr, val) \
|
||||
((cr) | (((val) << HD64461_LCDBBTMDR_SHIFT) & \
|
||||
(HD64461_LCDBBTMDR_MASK << HD64461_LCDBBTMDR_SHIFT)))
|
||||
#define HD64461_LCDBBTMDR_ON_SCREEN_TO_ON_SCREEN 0
|
||||
#define HD64461_LCDBBTMDR_ON_SCREEN_TO_OFF_SCREEN 1
|
||||
#define HD64461_LCDBBTMDR_OFF_SCREEN_TO_ON_SCREEN 3
|
||||
|
||||
#define HD64461_LCDBBTMDR_SCANDRCT 0x0001
|
||||
#define HD64461_LCDBBTMDR_SCANDRCT_RL_BT 0x1
|
||||
#define HD64461_LCDBBTMDR_SCANDRCT_LR_TB 0x0
|
||||
|
||||
/*
|
||||
* BitBLT Function
|
||||
*/
|
||||
#define HD64461_LCDC_BITBLT_SRCAND 0x0088
|
||||
#define HD64461_LCDC_BITBLT_SRCCOPY 0x00cc
|
||||
#define HD64461_LCDC_BITBLT_SRCINVERT 0x0066
|
||||
#define HD64461_LCDC_BITBLT_SRCPAINT 0x00ee
|
||||
#define HD64461_LCDC_BITBLT_PATCOPY 0x00f0
|
||||
#define HD64461_LCDC_BITBLT_PATINVERT 0x005a
|
||||
#define HD64461_LCDC_BITBLT_DSTINVERT 0x0055
|
||||
#define HD64461_LCDC_BITBLT_BLACKNESS 0x0000
|
||||
#define HD64461_LCDC_BITBLT_WHITENESS 0x00ff
|
||||
#define HD64461_LCDC_BITBLT_MASKEDSRCCOPY 0xccaa
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: console.c,v 1.2 2001/03/20 16:03:28 uch Exp $ */
|
||||
/* $NetBSD: console.c,v 1.3 2001/06/04 17:08:36 uch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2001 The NetBSD Foundation, Inc.
|
||||
|
|
@ -80,14 +80,38 @@ cdev_decl(com);
|
|||
cons_decl(com);
|
||||
|
||||
/* builtin video console */
|
||||
#if NBICONSDEV > 0
|
||||
#define biconscnpollc nullcnpollc
|
||||
cdev_decl(biconsdev);
|
||||
cons_decl(bicons);
|
||||
#endif
|
||||
|
||||
/* HD64461 video module */
|
||||
#if NHD64461IF > 0
|
||||
cons_decl(hd64461video_);
|
||||
#if NWSKBD > 0
|
||||
#define hd64461video_cngetc wskbd_cngetc
|
||||
#else
|
||||
int
|
||||
hd64461video_cngetc(dev_t dev)
|
||||
{
|
||||
printf("no input method. reboot me.\n");
|
||||
while (1)
|
||||
;
|
||||
/* NOTREACHED */
|
||||
}
|
||||
#endif
|
||||
#define hd64461video_cnputc wsdisplay_cnputc
|
||||
#define hd64461video_cnpollc nullcnpollc
|
||||
#endif
|
||||
|
||||
struct consdev constab[] = {
|
||||
#if NBICONSDEV > 0
|
||||
cons_init(bicons),
|
||||
#endif
|
||||
#if NHD64461IF > 0
|
||||
cons_init(hd64461video_),
|
||||
#endif
|
||||
#if NSCI > 0
|
||||
cons_init(sci),
|
||||
#endif
|
||||
|
|
@ -110,6 +134,8 @@ static void cn_nonprobe(struct consdev *);
|
|||
void
|
||||
consinit()
|
||||
{
|
||||
int serial_console = 1;
|
||||
|
||||
if (initialized)
|
||||
return;
|
||||
|
||||
|
|
@ -120,6 +146,13 @@ consinit()
|
|||
case BI_CNUSE_BUILTIN:
|
||||
#if NBICONSDEV > 0
|
||||
CN_ENABLE(bicons);
|
||||
serial_console = 0;
|
||||
#endif
|
||||
break;
|
||||
case BI_CNUSE_HD64461VIDEO:
|
||||
#if NHD64461IF > 0
|
||||
CN_ENABLE(hd64461video_);
|
||||
serial_console = 0;
|
||||
#endif
|
||||
break;
|
||||
case BI_CNUSE_SCI:
|
||||
|
|
@ -149,19 +182,20 @@ consinit()
|
|||
if (initialized)
|
||||
cninit();
|
||||
|
||||
if (bootinfo->bi_cnuse == BI_CNUSE_BUILTIN) {
|
||||
#if NPFCKBD > 0
|
||||
if (!serial_console)
|
||||
pfckbd_cnattach();
|
||||
#endif
|
||||
#if NHPCFB > 0
|
||||
|
||||
#if NHPCFB > 0 && NBICONSDEV > 0
|
||||
if (cn_tab->cn_putc == biconscnputc)
|
||||
hpcfb_cnattach(0);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
set_console(void (*putc_func)(dev_t, int),
|
||||
void (*probe_func)(struct consdev *))
|
||||
void (*probe_func)(struct consdev *))
|
||||
{
|
||||
struct consdev *cp;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: bootinfo.h,v 1.4 2001/03/15 17:30:56 uch Exp $ */
|
||||
/* $NetBSD: bootinfo.h,v 1.5 2001/06/04 17:08:36 uch Exp $ */
|
||||
|
||||
#include <hpc/hpc/bootinfo.h>
|
||||
|
||||
|
|
@ -6,3 +6,4 @@
|
|||
#define BI_CNUSE_SCI 2
|
||||
#define BI_CNUSE_SCIF 3
|
||||
#define BI_CNUSE_HD64461COM 4
|
||||
#define BI_CNUSE_HD64461VIDEO 5
|
||||
|
|
|
|||
Loading…
Reference in New Issue