diff --git a/sys/arch/powerpc/include/fpu.h b/sys/arch/powerpc/include/fpu.h
index e8cdb9c2dbfb..9285e254db45 100644
--- a/sys/arch/powerpc/include/fpu.h
+++ b/sys/arch/powerpc/include/fpu.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: fpu.h,v 1.1 1996/09/30 16:34:24 ws Exp $	*/
+/*	$NetBSD: fpu.h,v 1.2 1999/12/07 15:14:56 danw Exp $	*/
 
 /*-
  * Copyright (C) 1996 Wolfgang Solfrank.
@@ -33,37 +33,37 @@
 #ifndef	_MACHINE_FPU_H_
 #define	_MACHINE_FPU_H_
 
-#define	FPCSR_FX	0x80000000
-#define	FPCSR_FEX	0x40000000
-#define	FPCSR_VX	0x20000000
-#define	FPCSR_OX	0x10000000
-#define	FPCSR_UX	0x08000000
-#define	FPCSR_ZX	0x04000000
-#define	FPCSR_XX	0x02000000
-#define	FPCSR_VXSNAN	0x01000000
-#define	FPCSR_VXISI	0x00800000
-#define	FPCSR_VXIDI	0x00400000
-#define	FPCSR_VXZDZ	0x00200000
-#define	FPCSR_VXIMZ	0x00100000
-#define	FPCSR_VXVC	0x00080000
-#define	FPCSR_FR	0x00040000
-#define	FPCSR_FI	0x00020000
-#define	FPCSR_FPRF	0x0001f000
-#define	FPCSR_C		0x00010000
-#define	FPCSR_FPCC	0x0000f000
-#define	FPCSR_FL	0x00008000
-#define	FPCSR_FG	0x00004000
-#define	FPCSR_FE	0x00002000
-#define	FPCSR_FU	0x00001000
-#define	FPCSR_VXSOFT	0x00000400
-#define	FPCSR_VXSQRT	0x00000200
-#define	FPCSR_VXCVI	0x00000100
-#define	FPCSR_VE	0x00000080
-#define	FPCSR_OE	0x00000040
-#define	FPCSR_UE	0x00000020
-#define	FPCSR_ZE	0x00000010
-#define	FPCSR_XE	0x00000008
-#define	FPCSR_NI	0x00000004
-#define	FPCSR_RN	0x00000003
+#define	FPSCR_FX	0x80000000
+#define	FPSCR_FEX	0x40000000
+#define	FPSCR_VX	0x20000000
+#define	FPSCR_OX	0x10000000
+#define	FPSCR_UX	0x08000000
+#define	FPSCR_ZX	0x04000000
+#define	FPSCR_XX	0x02000000
+#define	FPSCR_VXSNAN	0x01000000
+#define	FPSCR_VXISI	0x00800000
+#define	FPSCR_VXIDI	0x00400000
+#define	FPSCR_VXZDZ	0x00200000
+#define	FPSCR_VXIMZ	0x00100000
+#define	FPSCR_VXVC	0x00080000
+#define	FPSCR_FR	0x00040000
+#define	FPSCR_FI	0x00020000
+#define	FPSCR_FPRF	0x0001f000
+#define	FPSCR_C		0x00010000
+#define	FPSCR_FPCC	0x0000f000
+#define	FPSCR_FL	0x00008000
+#define	FPSCR_FG	0x00004000
+#define	FPSCR_FE	0x00002000
+#define	FPSCR_FU	0x00001000
+#define	FPSCR_VXSOFT	0x00000400
+#define	FPSCR_VXSQRT	0x00000200
+#define	FPSCR_VXCVI	0x00000100
+#define	FPSCR_VE	0x00000080
+#define	FPSCR_OE	0x00000040
+#define	FPSCR_UE	0x00000020
+#define	FPSCR_ZE	0x00000010
+#define	FPSCR_XE	0x00000008
+#define	FPSCR_NI	0x00000004
+#define	FPSCR_RN	0x00000003
 
 #endif	/* _MACHINE_FPU_H_ */
diff --git a/sys/arch/powerpc/include/pcb.h b/sys/arch/powerpc/include/pcb.h
index 0b119a86b407..3fda1b3f781e 100644
--- a/sys/arch/powerpc/include/pcb.h
+++ b/sys/arch/powerpc/include/pcb.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: pcb.h,v 1.2 1998/11/22 21:21:32 ws Exp $	*/
+/*	$NetBSD: pcb.h,v 1.3 1999/12/07 15:14:56 danw Exp $	*/
 
 /*-
  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -45,7 +45,7 @@ struct pcb {
 #define	PCB_FPU		1	/* Process had FPU initialized */
 	struct fpu {
 		double fpr[32];
-		double fpcsr;	/* FPCSR stored as double for easier access */
+		double fpscr;	/* FPSCR stored as double for easier access */
 	} pcb_fpu;		/* Floating point processor */
 };
 
diff --git a/sys/arch/powerpc/powerpc/fpu.c b/sys/arch/powerpc/powerpc/fpu.c
index 46e723d93704..33cdaa2cf4ea 100644
--- a/sys/arch/powerpc/powerpc/fpu.c
+++ b/sys/arch/powerpc/powerpc/fpu.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: fpu.c,v 1.1 1996/09/30 16:34:44 ws Exp $	*/
+/*	$NetBSD: fpu.c,v 1.2 1999/12/07 15:14:57 danw Exp $	*/
 
 /*
  * Copyright (C) 1996 Wolfgang Solfrank.
@@ -52,7 +52,7 @@ enable_fpu(p)
 	}
 	asm volatile ("mfmsr %0; ori %1,%0,%2; mtmsr %1; isync"
 		      : "=r"(msr), "=r"(scratch) : "K"(PSL_FP));
-	asm volatile ("lfd 0,0(%0); mtfsf 0xff,0" :: "b"(&pcb->pcb_fpu.fpcsr));
+	asm volatile ("lfd 0,0(%0); mtfsf 0xff,0" :: "b"(&pcb->pcb_fpu.fpscr));
 	asm ("lfd 0,0(%0);"
 	     "lfd 1,8(%0);"
 	     "lfd 2,16(%0);"
@@ -129,6 +129,6 @@ save_fpu(p)
 	     "stfd 29,232(%0);"
 	     "stfd 30,240(%0);"
 	     "stfd 31,248(%0)" :: "b"(&pcb->pcb_fpu.fpr[0]));
-	asm volatile ("mffs 0; stfd 0,0(%0)" :: "b"(&pcb->pcb_fpu.fpcsr));
+	asm volatile ("mffs 0; stfd 0,0(%0)" :: "b"(&pcb->pcb_fpu.fpscr));
 	asm volatile ("mtmsr %0; isync" :: "r"(msr));
 }