Fix a bug that ichlpcib(4) maps I/O area incorrectly and then fails to attach
gpio. It might also fix ACPI related problem described in PR#48960: - The LPCIB_PCI_PMBASE and LPCIB_PCI_GPIO register are alike PCI BAR but not completely compatible with it. It's ok because the registers' addresses are out of BAR0-BAR5(0x10-0x24) and are located in the device-dependent header. The PMBASE and GPIO registers define the base address and the type but not describe the size. The size is fixed to 128bytes. So use pci_mapreg_submap(). - Make pci_mapreg_submap() extern again. - Fix the calculation of the map size in pci_mapreg_submap().
This commit is contained in:
msaitoh
parent
1a965b8777
commit
83c4f0e13c
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@ -1,4 +1,4 @@
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/* $NetBSD: ichlpcib.c,v 1.44 2014/12/15 13:29:42 msaitoh Exp $ */
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/* $NetBSD: ichlpcib.c,v 1.45 2014/12/26 05:09:03 msaitoh Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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@ -39,7 +39,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.44 2014/12/15 13:29:42 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.45 2014/12/26 05:09:03 msaitoh Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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@ -321,9 +321,14 @@ lpcibattach(device_t parent, device_t self, void *aux)
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* Part of our I/O registers are used as ACPI PM regs.
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* Since our ACPI subsystem accesses the I/O space directly so far,
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* we do not have to bother bus_space I/O map confliction.
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*
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* The PMBASE register is alike PCI BAR but not completely compatible
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* with it. The PMBASE define the base address and the type but
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* not describe the size.
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*/
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if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) {
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if (pci_mapreg_submap(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0,
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LPCIB_PCI_PM_SIZE, 0, &sc->sc_iot, &sc->sc_ioh, NULL,
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&sc->sc_iosize)) {
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aprint_error_dev(self, "can't map power management i/o space\n");
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return;
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}
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@ -1057,6 +1062,7 @@ lpcib_gpio_configure(device_t self)
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pcireg_t gpio_cntl;
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uint32_t use, io, bit;
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int pin, shift, base_reg, cntl_reg, reg;
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int rv;
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/* this implies ICH >= 6, and thus different mapreg */
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if (sc->sc_has_rcba) {
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@ -1073,11 +1079,16 @@ lpcib_gpio_configure(device_t self)
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/* Is GPIO enabled? */
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if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0)
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return;
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if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0,
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&sc->sc_gpio_iot, &sc->sc_gpio_ioh,
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NULL, &sc->sc_gpio_ios)) {
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aprint_error_dev(self, "can't map general purpose i/o space\n");
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/*
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* The GPIO_BASE register is alike PCI BAR but not completely
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* compatible with it. The PMBASE define the base address and the type
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* but not describe the size.
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*/
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rv = pci_mapreg_submap(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0,
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LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_iot, &sc->sc_gpio_ioh,
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NULL, &sc->sc_gpio_ios);
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if (rv != 0) {
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aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv);
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return;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: i82801lpcreg.h,v 1.11 2010/07/23 02:23:58 jakllsch Exp $ */
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/* $NetBSD: i82801lpcreg.h,v 1.12 2014/12/26 05:09:03 msaitoh Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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@ -40,6 +40,7 @@
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* PCI configuration registers
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*/
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#define LPCIB_PCI_PMBASE 0x40
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#define LPCIB_PCI_PM_SIZE 0x00000080
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#define LPCIB_PCI_ACPI_CNTL 0x44
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# define LPCIB_PCI_ACPI_CNTL_EN (1 << 4)
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/* GPIO config registers ICH6+ */
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@ -51,6 +52,7 @@
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#define LPCIB_PCI_TCO_CNTL 0x54
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/* GPIO config registers ICH0-ICH5 */
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#define LPCIB_PCI_GPIO_BASE 0x58
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#define LPCIB_PCI_GPIO_SIZE 0x00000080
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#define LPCIB_PCI_GPIO_CNTL 0x5c
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#define LPCIB_PCI_GPIO_CNTL_EN (1 << 4)
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#define LPCIB_PCI_PIRQA_ROUT 0x60
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_map.c,v 1.31 2014/10/16 12:31:23 riastradh Exp $ */
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/* $NetBSD: pci_map.c,v 1.32 2014/12/26 05:09:03 msaitoh Exp $ */
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/*-
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* Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.31 2014/10/16 12:31:23 riastradh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.32 2014/12/26 05:09:03 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -43,10 +43,6 @@ __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.31 2014/10/16 12:31:23 riastradh Exp $
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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static int pci_mapreg_submap(const struct pci_attach_args *, int, pcireg_t, int,
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bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *,
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bus_addr_t *, bus_size_t *);
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static int
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pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
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bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
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@ -282,7 +278,7 @@ pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type,
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handlep, basep, sizep);
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}
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static int
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int
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pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type,
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int busflags, bus_size_t maxsize, bus_size_t offset, bus_space_tag_t *tagp,
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bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep)
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@ -324,10 +320,10 @@ pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type,
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* pci_mapreg_map.
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*/
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maxsize = (maxsize && offset) ? maxsize : size;
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maxsize = (maxsize != 0) ? maxsize : size;
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base += offset;
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if ((maxsize < size && offset + maxsize <= size) || offset != 0)
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if ((size < maxsize) || (size < (offset + maxsize)))
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return 1;
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if (bus_space_map(tag, base, maxsize, busflags | flags, &handle))
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@ -1,4 +1,4 @@
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/* $NetBSD: pcivar.h,v 1.100 2014/10/16 12:31:23 riastradh Exp $ */
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/* $NetBSD: pcivar.h,v 1.101 2014/12/26 05:09:03 msaitoh Exp $ */
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/*
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* Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
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@ -269,6 +269,10 @@ int pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t,
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int pci_mapreg_map(const struct pci_attach_args *, int, pcireg_t, int,
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bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *,
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bus_size_t *);
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int pci_mapreg_submap(const struct pci_attach_args *, int, pcireg_t, int,
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bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *,
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bus_addr_t *, bus_size_t *);
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int pci_find_rom(const struct pci_attach_args *, bus_space_tag_t,
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bus_space_handle_t, bus_size_t,
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