add a prelimary implementation of MPC8245 EUMB I2C.
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nisimura
parent
55e31e2b6d
commit
82460723d2
@ -1,4 +1,4 @@
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/* $NetBSD: iic_eumb.c,v 1.2 2007/10/17 19:56:59 garbled Exp $ */
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/* $NetBSD: iic_eumb.c,v 1.3 2008/04/02 06:20:53 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -37,7 +37,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: iic_eumb.c,v 1.2 2007/10/17 19:56:59 garbled Exp $");
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__KERNEL_RCSID(0, "$NetBSD: iic_eumb.c,v 1.3 2008/04/02 06:20:53 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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@ -52,6 +52,7 @@ __KERNEL_RCSID(0, "$NetBSD: iic_eumb.c,v 1.2 2007/10/17 19:56:59 garbled Exp $")
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#include <sandpoint/sandpoint/eumbvar.h>
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void iic_bootstrap_init(void);
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int iic_seep_bootstrap_read(int, int, uint8_t *, size_t);
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static int iic_eumb_match(struct device *, struct cfdata *, void *);
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@ -74,6 +75,7 @@ static int motoi2c_send_stop(void *, int);
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static int motoi2c_initiate_xfer(void *, uint16_t, int);
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static int motoi2c_read_byte(void *, uint8_t *, int);
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static int motoi2c_write_byte(void *, uint8_t, int);
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static void wait4done(void);
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static struct i2c_controller motoi2c = {
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.ic_acquire_bus = motoi2c_acquire_bus,
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@ -86,28 +88,30 @@ static struct i2c_controller motoi2c = {
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};
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/*
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* MPC824x I2C controller seems to share a common design with
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* This I2C controller seems to share a common design with
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* i.MX/MC9328. Different names in bit field definition and
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* not suffered from document error.
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*/
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#define I2CADR 0x0000
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#define I2CFDR 0x0004
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#define I2CCR 0x0008
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#define I2CCR_MEN 0x80
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#define I2CCR_MIEN 0x40
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#define I2CCR_MSTA 0x20
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#define I2CCR_MTX 0x10
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#define I2CCR_TXAK 0x08
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#define I2CCR_RSTA 0x04
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#define I2CSR 0x000c
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#define I2CSR_MCF 0x80
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#define I2CSR_MBB 0x20
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#define I2CSR_MAL 0x10
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#define I2CSR_MIF 0x02
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#define I2CSR_RXAK 0x01
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#define I2CDR 0x0010
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#define CSR_READ(r) in32rb(0xfe003000 + (r))
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#define CSR_WRITE(r,v) out32rb(0xfe003000 + (r), (v))
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#define I2CADR 0x0000 /* my own I2C addr to respond for an external master */
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#define I2CFDR 0x0004 /* frequency devider */
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#define I2CCR 0x0008 /* control */
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#define CR_MEN 0x80 /* enable this HW */
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#define CR_MIEN 0x40 /* enable interrupt */
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#define CR_MSTA 0x20 /* 0->1 activates START, 1->0 makes STOP condition */
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#define CR_MTX 0x10 /* 1 for Tx, 0 for Rx */
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#define CR_TXAK 0x08 /* 1 makes no acknowledge when Rx */
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#define CR_RSTA 0x04 /* generate repeated START condition */
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#define I2CSR 0x000c /* status */
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#define SR_MCF 0x80 /* date transter has completed */
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#define SR_MBB 0x20 /* 1 before STOP condition is detected */
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#define SR_MAL 0x10 /* arbitration was lost */
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#define SR_MIF 0x02 /* indicates data transter completion */
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#define SR_RXAK 0x01
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#define I2CDR 0x0010 /* data */
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#define CSR_READ(r) in8rb(0xfc003000 + (r))
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#define CSR_WRITE(r,v) out8rb(0xfc003000 + (r), (v))
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#define CSR_WRITE4(r,v) out32rb(0xfc003000 + (r), (v))
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static int found;
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@ -136,11 +140,7 @@ iic_eumb_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_ioh = ioh;
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iba.iba_tag = &sc->sc_i2c;
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CSR_WRITE(I2CCR, 0x0);
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CSR_WRITE(I2CFDR, 0x0);
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CSR_WRITE(I2CADR, 127);
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CSR_WRITE(I2CSR, 0);
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CSR_WRITE(I2CCR, I2CCR_MEN);
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iic_bootstrap_init();
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#if 0
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/* not yet */
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config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print);
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@ -149,6 +149,17 @@ iic_eumb_attach(struct device *parent, struct device *self, void *aux)
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#endif
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}
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void
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iic_bootstrap_init()
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{
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CSR_WRITE(I2CCR, 0);
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CSR_WRITE4(I2CFDR, 0x1031); /* XXX magic XXX */
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CSR_WRITE(I2CADR, 0);
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CSR_WRITE(I2CSR, 0);
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CSR_WRITE(I2CCR, CR_MEN);
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}
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int
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iic_seep_bootstrap_read(int i2caddr, int offset, uint8_t *rvp, size_t len)
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{
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@ -156,21 +167,21 @@ iic_seep_bootstrap_read(int i2caddr, int offset, uint8_t *rvp, size_t len)
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uint8_t cmdbuf[1];
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if (motoi2c_acquire_bus(&motoi2c, I2C_F_POLL) != 0)
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return (-1);
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return -1;
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while (len) {
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addr = i2caddr + (offset >> 8);
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cmdbuf[0] = offset & 0xff;
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if (iic_exec(&motoi2c, I2C_OP_READ_WITH_STOP, addr,
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cmdbuf, 1, rvp, 1, I2C_F_POLL)) {
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motoi2c_release_bus(&motoi2c, I2C_F_POLL);
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return (-1);
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return -1;
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}
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len--;
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rvp++;
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offset++;
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}
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motoi2c_release_bus(&motoi2c, I2C_F_POLL);
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return (0);
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return 0;
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}
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static int
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@ -178,10 +189,11 @@ motoi2c_acquire_bus(void *v, int flags)
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{
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unsigned loop = 10;
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while (loop-- != 0 && CSR_READ(I2CSR) & I2CSR_MBB)
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/* loop */;
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while (--loop != 0 && (CSR_READ(I2CSR) & SR_MBB))
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DELAY(1);
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if (loop == 0)
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return -1;
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printf("bus acquired\n");
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return 0;
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}
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@ -190,50 +202,98 @@ motoi2c_release_bus(void *v, int flags)
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{
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unsigned loop = 10;
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CSR_WRITE(I2CCR, I2CCR_MEN);
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while (loop-- != 0 && CSR_READ(I2CSR) & I2CSR_MBB)
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/* loop */;
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while (--loop != 0 && (CSR_READ(I2CSR) & SR_MBB))
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DELAY(1);
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}
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static int
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motoi2c_send_start(void *v, int flags)
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{
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unsigned cr = CSR_READ(I2CCR);
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unsigned cr, sr;
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cr |= I2CCR_TXAK;
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cr = CSR_READ(I2CCR);
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cr |= CR_MSTA;
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CSR_WRITE(I2CCR, cr);
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/* not yet */
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do {
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sr = CSR_READ(I2CSR);
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if (sr & SR_MAL) {
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printf("moti2c_send_start() lost sync\n");
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sr &= ~SR_MAL;
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CSR_WRITE(I2CSR, sr);
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return -1;
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}
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} while ((sr & SR_MBB) == 0);
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printf("start sent\n");
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return 0;
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}
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static int
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motoi2c_send_stop(void *v, int flags)
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{
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unsigned cr = CSR_READ(I2CCR);
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unsigned cr;
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cr &= ~I2CCR_MSTA;
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cr = CSR_READ(I2CCR);
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cr &= ~CR_MSTA;
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CSR_WRITE(I2CCR, cr);
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/* not yet */
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(void)CSR_READ(I2CDR);
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printf("stop sent\n");
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return 0;
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}
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static int
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motoi2c_initiate_xfer(void *v, i2c_addr_t addr, int flags)
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{
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/* not yet */
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unsigned cr;
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cr = CSR_READ(I2CCR);
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if (flags & I2C_F_READ) {
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cr &= ~(CR_MTX | CR_TXAK);
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cr |= CR_RSTA;
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CSR_WRITE(I2CCR, cr);
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cr &= ~CR_RSTA;
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CSR_WRITE(I2CCR, cr);
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(void)CSR_READ(I2CDR);
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wait4done();
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return 0;
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}
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cr |= CR_MTX;
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CSR_WRITE(I2CCR, cr);
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return 0;
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}
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static int
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motoi2c_read_byte(void *v, uint8_t *bytep, int flags)
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{
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/* not yet */
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unsigned cr, val;
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if (flags & I2C_F_LAST) {
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cr = CSR_READ(I2CCR);
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cr |= CR_TXAK;
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CSR_WRITE(I2CCR, cr);
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}
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val = CSR_READ(I2CDR);
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wait4done();
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*bytep = val;
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return 0;
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}
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static int
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motoi2c_write_byte(void *v, uint8_t byte, int flags)
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{
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/* not yet */
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CSR_WRITE(I2CDR, byte);
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wait4done();
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return 0;
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}
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/* busy waiting for byte data transfer completion */
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static void
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wait4done()
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{
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unsigned sr;
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do {
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sr = CSR_READ(I2CSR);
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} while ((sr & SR_MIF) == 0);
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CSR_WRITE(I2CSR, sr &~ SR_MIF);
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}
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