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Add more-complete definitions of ICH GPIO-related registers. 

While here, fix a typo in a register number.
This commit is contained in:
jakllsch 2009-09-21 16:18:31 +00:00
parent 79b1421a0b
commit 81f8a1dcf0
1 changed files with 20 additions and 2 deletions
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22
sys/dev/ic/i82801lpcreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: i82801lpcreg.h,v 1.8 2008/04/28 20:23:50 martin Exp $ */
/* $NetBSD: i82801lpcreg.h,v 1.9 2009/09/21 16:18:31 jakllsch Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@ -42,8 +42,12 @@
#define LPCIB_PCI_PMBASE 0x40
#define LPCIB_PCI_ACPI_CNTL 0x44
# define LPCIB_PCI_ACPI_CNTL_EN (1 << 4)
/* GPIO config registers ICH6+ */
#define LPCIB_PCI_GPIO_BASE_ICH6 0x48
#define LPCIB_PCI_GPIO_CNTL_ICH6 0x4c
#define LPCIB_PCI_BIOS_CNTL 0x4e
#define LPCIB_PCI_TCO_CNTL 0x54
/* GPIO config registers ICH0-ICH5 */
#define LPCIB_PCI_GPIO_BASE 0x58
#define LPCIB_PCI_GPIO_CNTL 0x5c
#define LPCIB_PCI_PIRQA_ROUT 0x60
@ -69,7 +73,7 @@
#define LPCIB_PCI_MON5_TRP_RNG 0xc5
#define LPCIB_PCI_MON6_TRP_RNG 0xc6
#define LPCIB_PCI_MON7_TRP_RNG 0xc7
#define LPCIB_PCI_MON_TRP_MSK oxcc
#define LPCIB_PCI_MON_TRP_MSK 0xcc
#define LPCIB_PCI_GEN_CNTL 0xd0
#define LPCIB_ICH5_HPTC_EN 0x00020000
#define LPCIB_ICH5_HPTC_WIN_MASK 0x0000c000
@ -137,6 +141,20 @@
#define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */
# define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */
/*
* General Purpose I/O Registers
* (offset from GPIO_BASE)
*/
#define LPCIB_GPIO_GPIO_USE_SEL 0x00
#define LPCIB_GPIO_GP_IO_SEL 0x04
#define LPCIB_GPIO_GP_LVL 0x0c
#define LPCIB_GPIO_GPO_TTL 0x14
#define LPCIB_GPIO_GPO_BLINK 0x18
#define LPCIB_GPIO_GPI_INV 0x2c
#define LPCIB_GPIO_GPIO_USE_SEL2 0x30
#define LPCIB_GPIO_GP_IO_SEL2 0x34
#define LPCIB_GPIO_GP_LVL2 0x38
/*
* SMBus controller registers.
*/