From 801f52711125d8b052554513d088861de232b203 Mon Sep 17 00:00:00 2001 From: rumble Date: Thu, 30 Dec 2004 23:18:09 +0000 Subject: [PATCH] Prepend HPC3 macros universally with "HPC3_" to distinctly recognise the corresponding revision and maintain consistency with HPC1. No functional change intended. --- sys/arch/sgimips/hpc/haltwo.c | 46 ++-- sys/arch/sgimips/hpc/hpc.c | 130 ++++----- sys/arch/sgimips/hpc/hpcdma.c | 6 +- sys/arch/sgimips/hpc/hpcreg.h | 421 +++++++++++++++-------------- sys/arch/sgimips/hpc/if_sq.c | 69 +++-- sys/arch/sgimips/hpc/sqvar.h | 8 +- sys/arch/sgimips/sgimips/console.c | 6 +- 7 files changed, 348 insertions(+), 338 deletions(-) diff --git a/sys/arch/sgimips/hpc/haltwo.c b/sys/arch/sgimips/hpc/haltwo.c index 803dadb0d1db..46773189e5b6 100644 --- a/sys/arch/sgimips/hpc/haltwo.c +++ b/sys/arch/sgimips/hpc/haltwo.c @@ -1,4 +1,4 @@ -/* $NetBSD: haltwo.c,v 1.4 2004/10/29 12:57:16 yamt Exp $ */ +/* $NetBSD: haltwo.c,v 1.5 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 2003 Ilpo Ruotsalainen @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: haltwo.c,v 1.4 2004/10/29 12:57:16 yamt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: haltwo.c,v 1.5 2004/12/30 23:18:09 rumble Exp $"); #include #include @@ -233,7 +233,7 @@ haltwo_setup_dma(struct haltwo_softc *sc, struct haltwo_codec *codec, if (next_intr == segp->ds_len) { /* Generate intr after this DMA buffer */ - descp->hpc3_hdd_ctl |= HDD_CTL_INTR; + descp->hpc3_hdd_ctl |= HPC3_HDD_CTL_INTR; next_intr = blksize; } else next_intr -= segp->ds_len; @@ -278,19 +278,19 @@ haltwo_attach(struct device *parent, struct device *self, void *aux) sc->sc_dma_tag = haa->ha_dmat; if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_devoff, - HPC_PBUS_CH0_DEVREGS_SIZE, &sc->sc_ctl_sh)) { + HPC3_PBUS_CH0_DEVREGS_SIZE, &sc->sc_ctl_sh)) { aprint_error(": unable to map control registers\n"); return; } - if (bus_space_subregion(haa->ha_st, haa->ha_sh, HPC_PBUS_CH2_DEVREGS, - HPC_PBUS_CH2_DEVREGS_SIZE, &sc->sc_vol_sh)) { + if (bus_space_subregion(haa->ha_st, haa->ha_sh, HPC3_PBUS_CH2_DEVREGS, + HPC3_PBUS_CH2_DEVREGS_SIZE, &sc->sc_vol_sh)) { aprint_error(": unable to map volume registers\n"); return; } if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_dmaoff, - HPC_PBUS_DMAREGS_SIZE, &sc->sc_dma_sh)) { + HPC3_PBUS_DMAREGS_SIZE, &sc->sc_dma_sh)) { aprint_error(": unable to map DMA registers\n"); return; } @@ -327,9 +327,9 @@ haltwo_attach(struct device *parent, struct device *self, void *aux) } /* XXX Magic PBUS CFGDMA values from Linux HAL2 driver XXX */ - bus_space_write_4(haa->ha_st, haa->ha_sh, HPC_PBUS_CH0_CFGDMA, + bus_space_write_4(haa->ha_st, haa->ha_sh, HPC3_PBUS_CH0_CFGDMA, 0x8208844); - bus_space_write_4(haa->ha_st, haa->ha_sh, HPC_PBUS_CH1_CFGDMA, + bus_space_write_4(haa->ha_st, haa->ha_sh, HPC3_PBUS_CH1_CFGDMA, 0x8208844); /* Unmute output */ @@ -350,8 +350,8 @@ haltwo_intr(void *v) struct haltwo_softc *sc = v; int ret = 0; - if (bus_space_read_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL) - & HPC_PBUS_DMACTL_IRQ) { + if (bus_space_read_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL) + & HPC3_PBUS_DMACTL_IRQ) { sc->sc_dac.intr(sc->sc_dac.intr_arg); ret = 1; @@ -501,8 +501,8 @@ haltwo_halt_output(void *v) struct haltwo_softc *sc = v; /* Disable PBUS DMA */ - bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL, - HPC_PBUS_DMACTL_ACT_LD); + bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL, + HPC3_PBUS_DMACTL_ACT_LD); return (0); } @@ -731,8 +731,8 @@ haltwo_trigger_output(void *v, void *start, void *end, int blksize, } /* Disable PBUS DMA */ - bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL, - HPC_PBUS_DMACTL_ACT_LD); + bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL, + HPC3_PBUS_DMACTL_ACT_LD); /* Disable HAL2 codec DMA */ haltwo_read_indirect(sc, HAL2_IREG_DMA_PORT_EN, &tmp, NULL); @@ -750,20 +750,20 @@ haltwo_trigger_output(void *v, void *start, void *end, int blksize, " fifobeg = %d fifoend = %d\n", param->hw_channels, highwater, fifobeg, fifoend)); - ctrl = HPC_PBUS_DMACTL_RT - | HPC_PBUS_DMACTL_ACT_LD - | (highwater << HPC_PBUS_DMACTL_HIGHWATER_SHIFT) - | (fifobeg << HPC_PBUS_DMACTL_FIFOBEG_SHIFT) - | (fifoend << HPC_PBUS_DMACTL_FIFOEND_SHIFT); + ctrl = HPC3_PBUS_DMACTL_RT + | HPC3_PBUS_DMACTL_ACT_LD + | (highwater << HPC3_PBUS_DMACTL_HIGHWATER_SHIFT) + | (fifobeg << HPC3_PBUS_DMACTL_FIFOBEG_SHIFT) + | (fifoend << HPC3_PBUS_DMACTL_FIFOEND_SHIFT); /* Using PBUS CH0 for DAC DMA */ haltwo_write_indirect(sc, HAL2_IREG_DMA_DRV, 1, 0); /* HAL2 is ready for action, now setup PBUS for DMA transfer */ - bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_DP, + bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_DP, sc->sc_dac.dma_seg.ds_addr); - bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC_PBUS_CH0_CTL, - ctrl | HPC_PBUS_DMACTL_ACT); + bus_space_write_4(sc->sc_st, sc->sc_dma_sh, HPC3_PBUS_CH0_CTL, + ctrl | HPC3_PBUS_DMACTL_ACT); /* Both HAL2 and PBUS have been setup, now start it up */ haltwo_read_indirect(sc, HAL2_IREG_DMA_PORT_EN, &tmp, NULL); diff --git a/sys/arch/sgimips/hpc/hpc.c b/sys/arch/sgimips/hpc/hpc.c index 58ea61776c6b..ed0a2d051850 100644 --- a/sys/arch/sgimips/hpc/hpc.c +++ b/sys/arch/sgimips/hpc/hpc.c @@ -1,4 +1,4 @@ -/* $NetBSD: hpc.c,v 1.30 2004/12/30 02:35:41 rumble Exp $ */ +/* $NetBSD: hpc.c,v 1.31 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -35,7 +35,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.30 2004/12/30 02:35:41 rumble Exp $"); +__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.31 2004/12/30 23:18:09 rumble Exp $"); #include #include @@ -71,7 +71,7 @@ const struct hpc_device { { "zsc", HPC_BASE_ADDRESS_0, /* XXX Magic numbers */ - HPC_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, + HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 29, HPCDEV_IP22 | HPCDEV_IP24 }, @@ -91,13 +91,13 @@ const struct hpc_device { { "pckbc", HPC_BASE_ADDRESS_0, - HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, + HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 28, HPCDEV_IP22 | HPCDEV_IP24 }, { "sq", HPC_BASE_ADDRESS_0, - HPC_ENET_DEVREGS, HPC_ENET_REGS, + HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 3, HPCDEV_IP22 | HPCDEV_IP24 }, @@ -133,13 +133,13 @@ const struct hpc_device { { "wdsc", HPC_BASE_ADDRESS_0, - HPC_SCSI0_DEVREGS, HPC_SCSI0_REGS, + HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ HPCDEV_IP22 | HPCDEV_IP24 }, { "wdsc", HPC_BASE_ADDRESS_0, - HPC_SCSI1_DEVREGS, HPC_SCSI1_REGS, + HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ HPCDEV_IP22 }, @@ -157,13 +157,13 @@ const struct hpc_device { { "dsclock", HPC_BASE_ADDRESS_0, - HPC_PBUS_BBRAM, 0, + HPC3_PBUS_BBRAM, 0, -1, HPCDEV_IP22 | HPCDEV_IP24 }, { "haltwo", HPC_BASE_ADDRESS_0, - HPC_PBUS_CH0_DEVREGS, HPC_PBUS_DMAREGS, + HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ HPCDEV_IP22 | HPCDEV_IP24 }, @@ -253,68 +253,68 @@ static struct hpc_values hpc1_values = { static struct hpc_values hpc3_values = { .revision 3, - .scsi0_regs = HPC_SCSI0_REGS, - .scsi0_regs_size = HPC_SCSI0_REGS_SIZE, - .scsi0_cbp = HPC_SCSI0_CBP, - .scsi0_ndbp = HPC_SCSI0_NDBP, - .scsi0_bc = HPC_SCSI0_BC, - .scsi0_ctl = HPC_SCSI0_CTL, - .scsi0_gio = HPC_SCSI0_GIO, - .scsi0_dev = HPC_SCSI0_DEV, - .scsi0_dmacfg = HPC_SCSI0_DMACFG, - .scsi0_piocfg = HPC_SCSI0_PIOCFG, - .scsi1_regs = HPC_SCSI1_REGS, - .scsi1_regs_size = HPC_SCSI1_REGS_SIZE, - .scsi1_cbp = HPC_SCSI1_CBP, - .scsi1_ndbp = HPC_SCSI1_NDBP, - .scsi1_bc = HPC_SCSI1_BC, - .scsi1_ctl = HPC_SCSI1_CTL, - .scsi1_gio = HPC_SCSI1_GIO, - .scsi1_dev = HPC_SCSI1_DEV, - .scsi1_dmacfg = HPC_SCSI1_DMACFG, - .scsi1_piocfg = HPC_SCSI1_PIOCFG, - .dmactl_dir = HPC_DMACTL_DIR, - .dmactl_flush = HPC_DMACTL_FLUSH, - .dmactl_active = HPC_DMACTL_ACTIVE, - .dmactl_reset = HPC_DMACTL_RESET, - .enet_regs = HPC_ENET_REGS, - .enet_regs_size = HPC_ENET_REGS_SIZE, + .scsi0_regs = HPC3_SCSI0_REGS, + .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, + .scsi0_cbp = HPC3_SCSI0_CBP, + .scsi0_ndbp = HPC3_SCSI0_NDBP, + .scsi0_bc = HPC3_SCSI0_BC, + .scsi0_ctl = HPC3_SCSI0_CTL, + .scsi0_gio = HPC3_SCSI0_GIO, + .scsi0_dev = HPC3_SCSI0_DEV, + .scsi0_dmacfg = HPC3_SCSI0_DMACFG, + .scsi0_piocfg = HPC3_SCSI0_PIOCFG, + .scsi1_regs = HPC3_SCSI1_REGS, + .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, + .scsi1_cbp = HPC3_SCSI1_CBP, + .scsi1_ndbp = HPC3_SCSI1_NDBP, + .scsi1_bc = HPC3_SCSI1_BC, + .scsi1_ctl = HPC3_SCSI1_CTL, + .scsi1_gio = HPC3_SCSI1_GIO, + .scsi1_dev = HPC3_SCSI1_DEV, + .scsi1_dmacfg = HPC3_SCSI1_DMACFG, + .scsi1_piocfg = HPC3_SCSI1_PIOCFG, + .dmactl_dir = HPC3_DMACTL_DIR, + .dmactl_flush = HPC3_DMACTL_FLUSH, + .dmactl_active = HPC3_DMACTL_ACTIVE, + .dmactl_reset = HPC3_DMACTL_RESET, + .enet_regs = HPC3_ENET_REGS, + .enet_regs_size = HPC3_ENET_REGS_SIZE, .enet_intdelay = 0, .enet_intdelayval = 0, - .enetr_cbp = HPC_ENETR_CBP, - .enetr_ndbp = HPC_ENETR_NDBP, - .enetr_bc = HPC_ENETR_BC, - .enetr_ctl = HPC_ENETR_CTL, - .enetr_ctl_active = ENETR_CTL_ACTIVE, - .enetr_reset = HPC_ENETR_RESET, - .enetr_dmacfg = HPC_ENETR_DMACFG, - .enetr_piocfg = HPC_ENETR_PIOCFG, - .enetx_cbp = HPC_ENETX_CBP, - .enetx_ndbp = HPC_ENETX_NDBP, - .enetx_bc = HPC_ENETX_BC, - .enetx_ctl = HPC_ENETX_CTL, - .enetx_ctl_active = ENETX_CTL_ACTIVE, - .enetx_dev = HPC_ENETX_DEV, - .enetr_fifo = HPC_ENETR_FIFO, - .enetr_fifo_size = HPC_ENETR_FIFO_SIZE, - .enetx_fifo = HPC_ENETX_FIFO, - .enetx_fifo_size = HPC_ENETX_FIFO_SIZE, - .scsi0_devregs_size = HPC_SCSI0_DEVREGS_SIZE, - .scsi1_devregs_size = HPC_SCSI1_DEVREGS_SIZE, - .enet_devregs = HPC_ENET_DEVREGS, - .enet_devregs_size = HPC_ENET_DEVREGS_SIZE, - .pbus_fifo = HPC_PBUS_FIFO, - .pbus_fifo_size = HPC_PBUS_FIFO_SIZE, - .pbus_bbram = HPC_PBUS_BBRAM, + .enetr_cbp = HPC3_ENETR_CBP, + .enetr_ndbp = HPC3_ENETR_NDBP, + .enetr_bc = HPC3_ENETR_BC, + .enetr_ctl = HPC3_ENETR_CTL, + .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, + .enetr_reset = HPC3_ENETR_RESET, + .enetr_dmacfg = HPC3_ENETR_DMACFG, + .enetr_piocfg = HPC3_ENETR_PIOCFG, + .enetx_cbp = HPC3_ENETX_CBP, + .enetx_ndbp = HPC3_ENETX_NDBP, + .enetx_bc = HPC3_ENETX_BC, + .enetx_ctl = HPC3_ENETX_CTL, + .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, + .enetx_dev = HPC3_ENETX_DEV, + .enetr_fifo = HPC3_ENETR_FIFO, + .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, + .enetx_fifo = HPC3_ENETX_FIFO, + .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, + .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, + .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, + .enet_devregs = HPC3_ENET_DEVREGS, + .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, + .pbus_fifo = HPC3_PBUS_FIFO, + .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, + .pbus_bbram = HPC3_PBUS_BBRAM, .scsi_max_xfer = MAX_SCSI_XFER, .scsi_dma_segs = (MAX_SCSI_XFER / 8192), .scsi_dma_segs_size = 8192, .clk_freq = 100, - .dma_datain_cmd = HPC_DMACTL_ACTIVE, - .dma_dataout_cmd = (HPC_DMACTL_ACTIVE | HPC_DMACTL_DIR), - .scsi_dmactl_flush = HPC_DMACTL_FLUSH, - .scsi_dmactl_active = HPC_DMACTL_ACTIVE, - .scsi_dmactl_reset = HPC_DMACTL_RESET + .dma_datain_cmd = HPC3_DMACTL_ACTIVE, + .dma_dataout_cmd = (HPC3_DMACTL_ACTIVE | HPC3_DMACTL_DIR), + .scsi_dmactl_flush = HPC3_DMACTL_FLUSH, + .scsi_dmactl_active = HPC3_DMACTL_ACTIVE, + .scsi_dmactl_reset = HPC3_DMACTL_RESET }; diff --git a/sys/arch/sgimips/hpc/hpcdma.c b/sys/arch/sgimips/hpc/hpcdma.c index bfe7fa81f4b2..68d652de71fe 100644 --- a/sys/arch/sgimips/hpc/hpcdma.c +++ b/sys/arch/sgimips/hpc/hpcdma.c @@ -1,4 +1,4 @@ -/* $NetBSD: hpcdma.c,v 1.9 2003/12/29 06:33:57 sekiya Exp $ */ +/* $NetBSD: hpcdma.c,v 1.10 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 2001 Wayne Knowles @@ -44,7 +44,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: hpcdma.c,v 1.9 2003/12/29 06:33:57 sekiya Exp $"); +__KERNEL_RCSID(0, "$NetBSD: hpcdma.c,v 1.10 2004/12/30 23:18:09 rumble Exp $"); #include #include @@ -154,7 +154,7 @@ hpcdma_sglist_create(struct hpc_dma_softc *sc, bus_dmamap_t dmamap) if (sc->hpc->revision == 3) { hva->hpc3_hdd_bufptr = 0; - hva->hpc3_hdd_ctl = HDD_CTL_EOCHAIN; + hva->hpc3_hdd_ctl = HPC3_HDD_CTL_EOCHAIN; hva->hdd_descptr = 0; hva++; } else { diff --git a/sys/arch/sgimips/hpc/hpcreg.h b/sys/arch/sgimips/hpc/hpcreg.h index 7bb54c31d7e1..a531dd82d88a 100644 --- a/sys/arch/sgimips/hpc/hpcreg.h +++ b/sys/arch/sgimips/hpc/hpcreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: hpcreg.h,v 1.12 2004/12/30 02:35:42 rumble Exp $ */ +/* $NetBSD: hpcreg.h,v 1.13 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -61,13 +61,13 @@ struct hpc_dma_desc { /* * Control flags */ -#define HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ -#define HDD_CTL_EOPACKET 0x40000000 /* Ethernet: end of packet */ -#define HDD_CTL_INTR 0x20000000 /* Interrupt when finished */ -#define HDD_CTL_XMITDONE 0x00008000 /* Ethernet transmit done */ -#define HDD_CTL_OWN 0x00004000 /* CPU owns this frame */ +#define HPC3_HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ +#define HPC3_HDD_CTL_EOPACKET 0x40000000 /* Ethernet: end of packet */ +#define HPC3_HDD_CTL_INTR 0x20000000 /* Interrupt when finished */ +#define HPC3_HDD_CTL_XMITDONE 0x00008000 /* Ethernet transmit done */ +#define HPC3_HDD_CTL_OWN 0x00004000 /* CPU owns this frame */ -#define HDD_CTL_BYTECNT(x) ((x) & 0x3fff) /* Byte count: for ethernet +#define HPC3_HDD_CTL_BYTECNT(x) ((x) & 0x3fff) /* Byte count: for ethernet * rcv channel also doubles as * length of packet received */ @@ -81,301 +81,302 @@ struct hpc_dma_desc { * XXX: define register values as well as their offsets. * */ -#define HPC_PBUS_DMAREGS 0x00000000 /* DMA registers for PBus */ -#define HPC_PBUS_DMAREGS_SIZE 0x0000ffff /* channels 0 - 7 */ +#define HPC3_PBUS_DMAREGS 0x00000000 /* DMA registers for PBus */ +#define HPC3_PBUS_DMAREGS_SIZE 0x0000ffff /* channels 0 - 7 */ -#define HPC_PBUS_CH0_BP 0x00000000 /* Chan 0 Buffer Ptr */ -#define HPC_PBUS_CH0_DP 0x00000004 /* Chan 0 Descriptor Ptr */ -#define HPC_PBUS_CH0_CTL 0x00001000 /* Chan 0 Control Register */ +#define HPC3_PBUS_CH0_BP 0x00000000 /* Chan 0 Buffer Ptr */ +#define HPC3_PBUS_CH0_DP 0x00000004 /* Chan 0 Descriptor Ptr */ +#define HPC3_PBUS_CH0_CTL 0x00001000 /* Chan 0 Control Register */ -#define HPC_PBUS_CH1_BP 0x00002000 /* Chan 1 Buffer Ptr */ -#define HPC_PBUS_CH1_DP 0x00002004 /* Chan 1 Descriptor Ptr */ -#define HPC_PBUS_CH1_CTL 0x00003000 /* Chan 1 Control Register */ +#define HPC3_PBUS_CH1_BP 0x00002000 /* Chan 1 Buffer Ptr */ +#define HPC3_PBUS_CH1_DP 0x00002004 /* Chan 1 Descriptor Ptr */ +#define HPC3_PBUS_CH1_CTL 0x00003000 /* Chan 1 Control Register */ -#define HPC_PBUS_CH2_BP 0x00004000 /* Chan 2 Buffer Ptr */ -#define HPC_PBUS_CH2_DP 0x00004004 /* Chan 2 Descriptor Ptr */ -#define HPC_PBUS_CH2_CTL 0x00005000 /* Chan 2 Control Register */ +#define HPC3_PBUS_CH2_BP 0x00004000 /* Chan 2 Buffer Ptr */ +#define HPC3_PBUS_CH2_DP 0x00004004 /* Chan 2 Descriptor Ptr */ +#define HPC3_PBUS_CH2_CTL 0x00005000 /* Chan 2 Control Register */ -#define HPC_PBUS_CH3_BP 0x00006000 /* Chan 3 Buffer Ptr */ -#define HPC_PBUS_CH3_DP 0x00006004 /* Chan 3 Descriptor Ptr */ -#define HPC_PBUS_CH3_CTL 0x00007000 /* Chan 3 Control Register */ +#define HPC3_PBUS_CH3_BP 0x00006000 /* Chan 3 Buffer Ptr */ +#define HPC3_PBUS_CH3_DP 0x00006004 /* Chan 3 Descriptor Ptr */ +#define HPC3_PBUS_CH3_CTL 0x00007000 /* Chan 3 Control Register */ -#define HPC_PBUS_CH4_BP 0x00008000 /* Chan 4 Buffer Ptr */ -#define HPC_PBUS_CH4_DP 0x00008004 /* Chan 4 Descriptor Ptr */ -#define HPC_PBUS_CH4_CTL 0x00009000 /* Chan 4 Control Register */ +#define HPC3_PBUS_CH4_BP 0x00008000 /* Chan 4 Buffer Ptr */ +#define HPC3_PBUS_CH4_DP 0x00008004 /* Chan 4 Descriptor Ptr */ +#define HPC3_PBUS_CH4_CTL 0x00009000 /* Chan 4 Control Register */ -#define HPC_PBUS_CH5_BP 0x0000a000 /* Chan 5 Buffer Ptr */ -#define HPC_PBUS_CH5_DP 0x0000a004 /* Chan 5 Descriptor Ptr */ -#define HPC_PBUS_CH5_CTL 0x0000b000 /* Chan 5 Control Register */ +#define HPC3_PBUS_CH5_BP 0x0000a000 /* Chan 5 Buffer Ptr */ +#define HPC3_PBUS_CH5_DP 0x0000a004 /* Chan 5 Descriptor Ptr */ +#define HPC3_PBUS_CH5_CTL 0x0000b000 /* Chan 5 Control Register */ -#define HPC_PBUS_CH6_BP 0x0000c000 /* Chan 6 Buffer Ptr */ -#define HPC_PBUS_CH6_DP 0x0000c004 /* Chan 6 Descriptor Ptr */ -#define HPC_PBUS_CH6_CTL 0x0000d000 /* Chan 6 Control Register */ +#define HPC3_PBUS_CH6_BP 0x0000c000 /* Chan 6 Buffer Ptr */ +#define HPC3_PBUS_CH6_DP 0x0000c004 /* Chan 6 Descriptor Ptr */ +#define HPC3_PBUS_CH6_CTL 0x0000d000 /* Chan 6 Control Register */ -#define HPC_PBUS_CH7_BP 0x0000e000 /* Chan 7 Buffer Ptr */ -#define HPC_PBUS_CH7_DP 0x0000e004 /* Chan 7 Descriptor Ptr */ -#define HPC_PBUS_CH7_CTL 0x0000f000 /* Chan 7 Control Register */ +#define HPC3_PBUS_CH7_BP 0x0000e000 /* Chan 7 Buffer Ptr */ +#define HPC3_PBUS_CH7_DP 0x0000e004 /* Chan 7 Descriptor Ptr */ +#define HPC3_PBUS_CH7_CTL 0x0000f000 /* Chan 7 Control Register */ -#define HPC_SCSI0_REGS 0x00010000 /* SCSI channel 0 registers */ -#define HPC_SCSI0_REGS_SIZE 0x00001fff +#define HPC3_SCSI0_REGS 0x00010000 /* SCSI channel 0 registers */ +#define HPC3_SCSI0_REGS_SIZE 0x00001fff -#define HPC_SCSI0_CBP 0x00000000 /* Current buffer ptr */ -#define HPC_SCSI0_NDBP 0x00000004 /* Next descriptor ptr */ +#define HPC3_SCSI0_CBP 0x00000000 /* Current buffer ptr */ +#define HPC3_SCSI0_NDBP 0x00000004 /* Next descriptor ptr */ -#define HPC_SCSI0_BC 0x00001000 /* DMA byte count & flags */ -#define HPC_SCSI0_CTL 0x00001004 /* DMA control flags */ -#define HPC_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ -#define HPC_SCSI0_DEV 0x0000100c /* Device DMA FIFO pointer */ -#define HPC_SCSI0_DMACFG 0x00001010 /* DMA configururation */ -#define HPC_SCSI0_PIOCFG 0x00001014 /* PIO configururation */ +#define HPC3_SCSI0_BC 0x00001000 /* DMA byte count & flags */ +#define HPC3_SCSI0_CTL 0x00001004 /* DMA control flags */ +#define HPC3_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ +#define HPC3_SCSI0_DEV 0x0000100c /* Device DMA FIFO pointer */ +#define HPC3_SCSI0_DMACFG 0x00001010 /* DMA configururation */ +#define HPC3_SCSI0_PIOCFG 0x00001014 /* PIO configururation */ -#define HPC_SCSI1_REGS 0x00012000 /* SCSI channel 1 registers */ -#define HPC_SCSI1_REGS_SIZE 0x00001fff +#define HPC3_SCSI1_REGS 0x00012000 /* SCSI channel 1 registers */ +#define HPC3_SCSI1_REGS_SIZE 0x00001fff -#define HPC_SCSI1_CBP 0x00000000 /* Current buffer ptr */ -#define HPC_SCSI1_NDBP 0x00000004 /* Next descriptor ptr */ +#define HPC3_SCSI1_CBP 0x00000000 /* Current buffer ptr */ +#define HPC3_SCSI1_NDBP 0x00000004 /* Next descriptor ptr */ -#define HPC_SCSI1_BC 0x00001000 /* DMA byte count & flags */ -#define HPC_SCSI1_CTL 0x00001004 /* DMA control flags */ -#define HPC_SCSI1_GIO 0x00001008 /* GIO DMA FIFO pointer */ -#define HPC_SCSI1_DEV 0x0000100c /* Device DMA FIFO pointer */ -#define HPC_SCSI1_DMACFG 0x00001010 /* DMA configururation */ -#define HPC_SCSI1_PIOCFG 0x00001014 /* PIO configururation */ +#define HPC3_SCSI1_BC 0x00001000 /* DMA byte count & flags */ +#define HPC3_SCSI1_CTL 0x00001004 /* DMA control flags */ +#define HPC3_SCSI1_GIO 0x00001008 /* GIO DMA FIFO pointer */ +#define HPC3_SCSI1_DEV 0x0000100c /* Device DMA FIFO pointer */ +#define HPC3_SCSI1_DMACFG 0x00001010 /* DMA configururation */ +#define HPC3_SCSI1_PIOCFG 0x00001014 /* PIO configururation */ /* These are only valid for SCSI/ENETR, PBUS uses different definitions */ -#define HPC_DMACTL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ -#define HPC_DMACTL_ENDIAN 0x02 /* DMA endian mode, 0=BE, 1=LE */ -#define HPC_DMACTL_DIR 0x04 /* DMA direction, 0=dev->mem, 1=mem->dev */ -#define HPC_DMACTL_FLUSH 0x08 /* Flush DMA FIFO's */ -#define HPC_DMACTL_ACTIVE 0x10 /* DMA channel is active */ -#define HPC_DMACTL_AMASK 0x20 /* DMA active inhibits PIO */ -#define HPC_DMACTL_RESET 0x40 /* Resets dma channel and external controller */ -#define HPC_DMACTL_PERR 0x80 /* Parity error on interface to controller */ +#define HPC3_DMACTL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ +#define HPC3_DMACTL_ENDIAN 0x02 /* DMA endian mode, 0=BE, 1=LE */ +#define HPC3_DMACTL_DIR 0x04 /* DMA direction, 0=dev->mem, 1=mem->dev */ +#define HPC3_DMACTL_FLUSH 0x08 /* Flush DMA FIFO's */ +#define HPC3_DMACTL_ACTIVE 0x10 /* DMA channel is active */ +#define HPC3_DMACTL_AMASK 0x20 /* DMA active inhibits PIO */ +#define HPC3_DMACTL_RESET 0x40 /* Resets dma channel and external controller */ +#define HPC3_DMACTL_PERR 0x80 /* Parity error on interface to controller */ /* HPC_PBUS_CHx_CTL read: */ -#define HPC_PBUS_DMACTL_IRQ 0x01 /* IRQ asserted, DMA done */ -#define HPC_PBUS_DMACTL_ISACT 0x02 /* DMA channel is active */ +#define HPC3_PBUS_DMACTL_IRQ 0x01 /* IRQ asserted, DMA done */ +#define HPC3_PBUS_DMACTL_ISACT 0x02 /* DMA channel is active */ + /* HPC_PBUS_CHx_CTL write: */ -#define HPC_PBUS_DMACTL_ENDIAN 0x02 /* DMA endianness, 0=BE 1=LE */ -#define HPC_PBUS_DMACTL_RECEIVE 0x04 /* DMA direction, 1=dev->mem, 0=mem->dev */ -#define HPC_PBUS_DMACTL_FLUSH 0x08 /* Flush DMA FIFO */ -#define HPC_PBUS_DMACTL_ACT 0x10 /* Activate DMA channel */ -#define HPC_PBUS_DMACTL_ACT_LD 0x20 /* Load enable for ACT */ -#define HPC_PBUS_DMACTL_RT 0x40 /* Enable real time GIO service for DMA */ -#define HPC_PBUS_DMACTL_HIGHWATER_SHIFT 8 -#define HPC_PBUS_DMACTL_FIFOBEG_SHIFT 16 -#define HPC_PBUS_DMACTL_FIFOEND_SHIFT 24 +#define HPC3_PBUS_DMACTL_ENDIAN 0x02 /* DMA endianness, 0=BE 1=LE */ +#define HPC3_PBUS_DMACTL_RECEIVE 0x04 /* DMA direction, 1=dev->mem, 0=mem->dev*/ +#define HPC3_PBUS_DMACTL_FLUSH 0x08 /* Flush DMA FIFO */ +#define HPC3_PBUS_DMACTL_ACT 0x10 /* Activate DMA channel */ +#define HPC3_PBUS_DMACTL_ACT_LD 0x20 /* Load enable for ACT */ +#define HPC3_PBUS_DMACTL_RT 0x40 /* Enable real time GIO service for DMA */ +#define HPC3_PBUS_DMACTL_HIGHWATER_SHIFT 8 +#define HPC3_PBUS_DMACTL_FIFOBEG_SHIFT 16 +#define HPC3_PBUS_DMACTL_FIFOEND_SHIFT 24 -#define HPC_ENET_REGS 0x00014000 /* Ethernet registers */ -#define HPC_ENET_REGS_SIZE 0x00003fff +#define HPC3_ENET_REGS 0x00014000 /* Ethernet registers */ +#define HPC3_ENET_REGS_SIZE 0x00003fff -#define HPC_ENETR_CBP 0x00000000 /* Recv: Current buffer ptr */ -#define HPC_ENETR_NDBP 0x00000004 /* Recv: Next descriptor ptr */ +#define HPC3_ENETR_CBP 0x00000000 /* Recv: Current buffer ptr */ +#define HPC3_ENETR_NDBP 0x00000004 /* Recv: Next descriptor ptr */ -#define HPC_ENETR_BC 0x00001000 /* Recv: DMA byte cnt/flags */ -#define HPC_ENETR_CTL 0x00001004 /* Recv: DMA control flags */ +#define HPC3_ENETR_BC 0x00001000 /* Recv: DMA byte cnt/flags */ +#define HPC3_ENETR_CTL 0x00001004 /* Recv: DMA control flags */ -#define ENETR_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ -#define ENETR_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ -#define ENETR_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ -#define ENETR_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ -#define ENETR_CTL_ACTIVE 0x0200 /* DMA channel active? */ -#define ENETR_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ -#define ENETR_CTL_RBO 0x0800 /* Recv buffer overflow */ +#define HPC3_ENETR_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ +#define HPC3_ENETR_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ +#define HPC3_ENETR_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ +#define HPC3_ENETR_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ +#define HPC3_ENETR_CTL_ACTIVE 0x0200 /* DMA channel active? */ +#define HPC3_ENETR_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ +#define HPC3_ENETR_CTL_RBO 0x0800 /* Recv buffer overflow */ -#define HPC_ENETR_GIO 0x00001008 /* Recv: GIO DMA FIFO ptr */ -#define HPC_ENETR_DEV 0x0000100c /* Recv: Device DMA FIFO ptr */ -#define HPC_ENETR_RESET 0x00001014 /* Recv: Ethernet chip reset */ +#define HPC3_ENETR_GIO 0x00001008 /* Recv: GIO DMA FIFO ptr */ +#define HPC3_ENETR_DEV 0x0000100c /* Recv: Device DMA FIFO ptr */ +#define HPC3_ENETR_RESET 0x00001014 /* Recv: Ethernet chip reset */ -#define ENETR_RESET_CH 0x0001 /* Reset controller & chan */ -#define ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ -#define ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ -#define ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ +#define HPC3_ENETR_RESET_CH 0x0001 /* Reset controller & chan */ +#define HPC3_ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ +#define HPC3_ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ +#define HPC3_ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ -#define HPC_ENETR_DMACFG 0x00001018 /* Recv: DMA configururation */ +#define HPC3_ENETR_DMACFG 0x00001018 /* Recv: DMA configururation */ -#define ENETR_DMACFG_D1 0x0000f /* DMA D1 state cycles */ -#define ENETR_DMACFG_D2 0x000f0 /* DMA D2 state cycles */ -#define ENETR_DMACFG_D3 0x00f00 /* DMA D3 state cycles */ -#define ENETR_DMACFG_WRCTL 0x01000 /* Enable IPG write */ +#define HPC3_ENETR_DMACFG_D1 0x0000f /* DMA D1 state cycles */ +#define HPC3_ENETR_DMACFG_D2 0x000f0 /* DMA D2 state cycles */ +#define HPC3_ENETR_DMACFG_D3 0x00f00 /* DMA D3 state cycles */ +#define HPC3_ENETR_DMACFG_WRCTL 0x01000 /* Enable IPG write */ /* * The following three bits work around bugs in the Seeq 8003; if you * don't set them, the Seeq gets wonky pretty often. */ -#define ENETR_DMACFG_FIX_RXDC 0x02000 /* Clear EOP bits on RXDC */ -#define ENETR_DMACFG_FIX_EOP 0x04000 /* Enable rxintr timeout */ -#define ENETR_DMACFG_FIX_INTR 0x08000 /* Enable EOP timeout */ -#define ENETR_DMACFG_TIMO 0x30000 /* Timeout for above two */ +#define HPC3_ENETR_DMACFG_FIX_RXDC 0x02000 /* Clear EOP bits on RXDC */ +#define HPC3_ENETR_DMACFG_FIX_EOP 0x04000 /* Enable rxintr timeout */ +#define HPC3_ENETR_DMACFG_FIX_INTR 0x08000 /* Enable EOP timeout */ +#define HPC3_ENETR_DMACFG_TIMO 0x30000 /* Timeout for above two */ -#define HPC_ENETR_PIOCFG 0x0000101c /* Recv: PIO configururation */ +#define HPC3_ENETR_PIOCFG 0x0000101c /* Recv: PIO configururation */ -#define HPC_ENETX_CBP 0x00002000 /* Xmit: Current buffer ptr */ -#define HPC_ENETX_NDBP 0x00002004 /* Xmit: Next descriptor ptr */ +#define HPC3_ENETX_CBP 0x00002000 /* Xmit: Current buffer ptr */ +#define HPC3_ENETX_NDBP 0x00002004 /* Xmit: Next descriptor ptr */ -#define HPC_ENETX_BC 0x00003000 /* Xmit: DMA byte cnt/flags */ -#define HPC_ENETX_CTL 0x00003004 /* Xmit: DMA control flags */ +#define HPC3_ENETX_BC 0x00003000 /* Xmit: DMA byte cnt/flags */ +#define HPC3_ENETX_CTL 0x00003004 /* Xmit: DMA control flags */ -#define ENETX_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ -#define ENETX_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ -#define ENETX_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ -#define ENETX_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ -#define ENETX_CTL_ACTIVE 0x0200 /* DMA channel active? */ -#define ENETX_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ -#define ENETX_CTL_RBO 0x0800 /* Recv buffer overflow */ +#define HPC3_ENETX_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ +#define HPC3_ENETX_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ +#define HPC3_ENETX_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ +#define HPC3_ENETX_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ +#define HPC3_ENETX_CTL_ACTIVE 0x0200 /* DMA channel active? */ +#define HPC3_ENETX_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ +#define HPC3_ENETX_CTL_RBO 0x0800 /* Recv buffer overflow */ -#define HPC_ENETX_GIO 0x00003008 /* Xmit: GIO DMA FIFO ptr */ -#define HPC_ENETX_DEV 0x0000300c /* Xmit: Device DMA FIFO ptr */ +#define HPC3_ENETX_GIO 0x00003008 /* Xmit: GIO DMA FIFO ptr */ +#define HPC3_ENETX_DEV 0x0000300c /* Xmit: Device DMA FIFO ptr */ -#define HPC_PBUS_FIFO 0x00020000 /* PBus DMA FIFO */ -#define HPC_PBUS_FIFO_SIZE 0x00007fff /* PBus DMA FIFO size */ +#define HPC3_PBUS_FIFO 0x00020000 /* PBus DMA FIFO */ +#define HPC3_PBUS_FIFO_SIZE 0x00007fff /* PBus DMA FIFO size */ -#define HPC_SCSI0_FIFO 0x00028000 /* SCSI0 DMA FIFO */ -#define HPC_SCSI0_FIFO_SIZE 0x00001fff /* SCSI0 DMA FIFO size */ +#define HPC3_SCSI0_FIFO 0x00028000 /* SCSI0 DMA FIFO */ +#define HPC3_SCSI0_FIFO_SIZE 0x00001fff /* SCSI0 DMA FIFO size */ -#define HPC_SCSI1_FIFO 0x0002a000 /* SCSI1 DMA FIFO */ -#define HPC_SCSI1_FIFO_SIZE 0x00001fff /* SCSI1 DMA FIFO size */ +#define HPC3_SCSI1_FIFO 0x0002a000 /* SCSI1 DMA FIFO */ +#define HPC3_SCSI1_FIFO_SIZE 0x00001fff /* SCSI1 DMA FIFO size */ -#define HPC_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ -#define HPC_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ +#define HPC3_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ +#define HPC3_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ -#define HPC_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ -#define HPC_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ +#define HPC3_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ +#define HPC3_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ /* * HPCBUG: The interrupt status is split amongst two registers, and they're * not even consecutive in the HPC address space. This is documented as a * bug by SGI. */ -#define HPC_INTRSTAT_40 0x00030000 /* Interrupt stat, bits 4:0 */ -#define HPC_INTRSTAT_95 0x0003000c /* Interrupt stat, bits 9:5 */ +#define HPC3_INTRSTAT_40 0x00030000 /* Interrupt stat, bits 4:0 */ +#define HPC3_INTRSTAT_95 0x0003000c /* Interrupt stat, bits 9:5 */ -#define HPC_GIO_MISC 0x00030004 /* GIO64 misc register */ +#define HPC3_GIO_MISC 0x00030004 /* GIO64 misc register */ -#define HPC_EEPROM_DATA 0x00030008 /* Serial EEPROM data reg. */ +#define HPC3_EEPROM_DATA 0x00030008 /* Serial EEPROM data reg. */ -#define HPC_GIO_BUSERR 0x00030010 /* GIO64 bus error intr stat */ +#define HPC3_GIO_BUSERR 0x00030010 /* GIO64 bus error intr stat */ -#define HPC_SCSI0_DEVREGS 0x00044000 /* SCSI channel 0 chip regs */ -#define HPC_SCSI0_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ +#define HPC3_SCSI0_DEVREGS 0x00044000 /* SCSI channel 0 chip regs */ +#define HPC3_SCSI0_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ -#define HPC_SCSI1_DEVREGS 0x0004c000 /* SCSI channel 1 chip regs */ -#define HPC_SCSI1_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ +#define HPC3_SCSI1_DEVREGS 0x0004c000 /* SCSI channel 1 chip regs */ +#define HPC3_SCSI1_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ -#define HPC_ENET_DEVREGS 0x00054000 /* Ethernet chip registers */ -#define HPC_ENET_DEVREGS_SIZE 0x000004ff /* Size of chip registers */ +#define HPC3_ENET_DEVREGS 0x00054000 /* Ethernet chip registers */ +#define HPC3_ENET_DEVREGS_SIZE 0x000004ff /* Size of chip registers */ -#define HPC_PBUS_DEVREGS 0x00054000 /* PBus PIO chip registers */ -#define HPC_PBUS_DEVREGS_SIZE 0x000003ff /* PBus PIO chip registers */ +#define HPC3_PBUS_DEVREGS 0x00054000 /* PBus PIO chip registers */ +#define HPC3_PBUS_DEVREGS_SIZE 0x000003ff /* PBus PIO chip registers */ -#define HPC_PBUS_CH0_DEVREGS 0x00058000 /* PBus ch. 0 chip registers */ -#define HPC_PBUS_CH0_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH0_DEVREGS 0x00058000 /* PBus ch. 0 chip registers */ +#define HPC3_PBUS_CH0_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH1_DEVREGS 0x00058400 /* PBus ch. 1 chip registers */ -#define HPC_PBUS_CH1_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH1_DEVREGS 0x00058400 /* PBus ch. 1 chip registers */ +#define HPC3_PBUS_CH1_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH2_DEVREGS 0x00058800 /* PBus ch. 2 chip registers */ -#define HPC_PBUS_CH2_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH2_DEVREGS 0x00058800 /* PBus ch. 2 chip registers */ +#define HPC3_PBUS_CH2_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH3_DEVREGS 0x00058c00 /* PBus ch. 3 chip registers */ -#define HPC_PBUS_CH3_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH3_DEVREGS 0x00058c00 /* PBus ch. 3 chip registers */ +#define HPC3_PBUS_CH3_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH4_DEVREGS 0x00059000 /* PBus ch. 4 chip registers */ -#define HPC_PBUS_CH4_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH4_DEVREGS 0x00059000 /* PBus ch. 4 chip registers */ +#define HPC3_PBUS_CH4_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH5_DEVREGS 0x00059400 /* PBus ch. 5 chip registers */ -#define HPC_PBUS_CH5_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH5_DEVREGS 0x00059400 /* PBus ch. 5 chip registers */ +#define HPC3_PBUS_CH5_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH6_DEVREGS 0x00059800 /* PBus ch. 6 chip registers */ -#define HPC_PBUS_CH6_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH6_DEVREGS 0x00059800 /* PBus ch. 6 chip registers */ +#define HPC3_PBUS_CH6_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH7_DEVREGS 0x00059c00 /* PBus ch. 7 chip registers */ -#define HPC_PBUS_CH7_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH7_DEVREGS 0x00059c00 /* PBus ch. 7 chip registers */ +#define HPC3_PBUS_CH7_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH8_DEVREGS 0x0005a000 /* PBus ch. 8 chip registers */ -#define HPC_PBUS_CH8_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH8_DEVREGS 0x0005a000 /* PBus ch. 8 chip registers */ +#define HPC3_PBUS_CH8_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH9_DEVREGS 0x0005a400 /* PBus ch. 9 chip registers */ -#define HPC_PBUS_CH9_DEVREGS_SIZE 0x03ff +#define HPC3_PBUS_CH9_DEVREGS 0x0005a400 /* PBus ch. 9 chip registers */ +#define HPC3_PBUS_CH9_DEVREGS_SIZE 0x03ff -#define HPC_PBUS_CH8_DEVREGS_2 0x0005a800 /* PBus ch. 8 chip registers */ -#define HPC_PBUS_CH8_DEVREGS_2_SIZE 0x03ff +#define HPC3_PBUS_CH8_DEVREGS_2 0x0005a800 /* PBus ch. 8 chip registers */ +#define HPC3_PBUS_CH8_DEVREGS_2_SIZE 0x03ff -#define HPC_PBUS_CH9_DEVREGS_2 0x0005ac00 /* PBus ch. 9 chip registers */ -#define HPC_PBUS_CH9_DEVREGS_2_SIZE 0x03ff +#define HPC3_PBUS_CH9_DEVREGS_2 0x0005ac00 /* PBus ch. 9 chip registers */ +#define HPC3_PBUS_CH9_DEVREGS_2_SIZE 0x03ff -#define HPC_PBUS_CH8_DEVREGS_3 0x0005b000 /* PBus ch. 8 chip registers */ -#define HPC_PBUS_CH8_DEVREGS_3_SIZE 0x03ff +#define HPC3_PBUS_CH8_DEVREGS_3 0x0005b000 /* PBus ch. 8 chip registers */ +#define HPC3_PBUS_CH8_DEVREGS_3_SIZE 0x03ff -#define HPC_PBUS_CH9_DEVREGS_3 0x0005b400 /* PBus ch. 9 chip registers */ -#define HPC_PBUS_CH9_DEVREGS_3_SIZE 0x03ff +#define HPC3_PBUS_CH9_DEVREGS_3 0x0005b400 /* PBus ch. 9 chip registers */ +#define HPC3_PBUS_CH9_DEVREGS_3_SIZE 0x03ff -#define HPC_PBUS_CH8_DEVREGS_4 0x0005b800 /* PBus ch. 8 chip registers */ -#define HPC_PBUS_CH8_DEVREGS_4_SIZE 0x03ff +#define HPC3_PBUS_CH8_DEVREGS_4 0x0005b800 /* PBus ch. 8 chip registers */ +#define HPC3_PBUS_CH8_DEVREGS_4_SIZE 0x03ff -#define HPC_PBUS_CH9_DEVREGS_4 0x0005bc00 /* PBus ch. 9 chip registers */ -#define HPC_PBUS_CH9_DEVREGS_4_SIZE 0x03ff +#define HPC3_PBUS_CH9_DEVREGS_4 0x0005bc00 /* PBus ch. 9 chip registers */ +#define HPC3_PBUS_CH9_DEVREGS_4_SIZE 0x03ff -#define HPC_PBUS_CFGDMA_REGS 0x0005c000 /* PBus DMA config registers */ -#define HPC_PBUS_CFGDMA_REGS_SIZE 0x0fff +#define HPC3_PBUS_CFGDMA_REGS 0x0005c000 /* PBus DMA config registers */ +#define HPC3_PBUS_CFGDMA_REGS_SIZE 0x0fff -#define HPC_PBUS_CH0_CFGDMA 0x0005c000 /* PBus Ch. 0 DMA config */ -#define HPC_PBUS_CH0_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH0_CFGDMA 0x0005c000 /* PBus Ch. 0 DMA config */ +#define HPC3_PBUS_CH0_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH1_CFGDMA 0x0005c200 /* PBus Ch. 1 DMA config */ -#define HPC_PBUS_CH1_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH1_CFGDMA 0x0005c200 /* PBus Ch. 1 DMA config */ +#define HPC3_PBUS_CH1_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH2_CFGDMA 0x0005c400 /* PBus Ch. 2 DMA config */ -#define HPC_PBUS_CH2_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH2_CFGDMA 0x0005c400 /* PBus Ch. 2 DMA config */ +#define HPC3_PBUS_CH2_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH3_CFGDMA 0x0005c600 /* PBus Ch. 3 DMA config */ -#define HPC_PBUS_CH3_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH3_CFGDMA 0x0005c600 /* PBus Ch. 3 DMA config */ +#define HPC3_PBUS_CH3_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH4_CFGDMA 0x0005c800 /* PBus Ch. 4 DMA config */ -#define HPC_PBUS_CH4_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH4_CFGDMA 0x0005c800 /* PBus Ch. 4 DMA config */ +#define HPC3_PBUS_CH4_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH5_CFGDMA 0x0005ca00 /* PBus Ch. 5 DMA config */ -#define HPC_PBUS_CH5_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH5_CFGDMA 0x0005ca00 /* PBus Ch. 5 DMA config */ +#define HPC3_PBUS_CH5_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH6_CFGDMA 0x0005cc00 /* PBus Ch. 6 DMA config */ -#define HPC_PBUS_CH6_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH6_CFGDMA 0x0005cc00 /* PBus Ch. 6 DMA config */ +#define HPC3_PBUS_CH6_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CH7_CFGDMA 0x0005ce00 /* PBus Ch. 7 DMA config */ -#define HPC_PBUS_CH7_CFGDMA_SIZE 0x01ff +#define HPC3_PBUS_CH7_CFGDMA 0x0005ce00 /* PBus Ch. 7 DMA config */ +#define HPC3_PBUS_CH7_CFGDMA_SIZE 0x01ff -#define HPC_PBUS_CFGPIO_REGS 0x0005d000 /* PBus PIO config registers */ -#define HPC_PBUS_CFGPIO_REGS_SIZE 0x0fff +#define HPC3_PBUS_CFGPIO_REGS 0x0005d000 /* PBus PIO config registers */ +#define HPC3_PBUS_CFGPIO_REGS_SIZE 0x0fff -#define HPC_PBUS_CH0_CFGPIO 0x0005d000 /* PBus Ch. 0 PIO config */ -#define HPC_PBUS_CH1_CFGPIO 0x0005d100 /* PBus Ch. 1 PIO config */ -#define HPC_PBUS_CH2_CFGPIO 0x0005d200 /* PBus Ch. 2 PIO config */ -#define HPC_PBUS_CH3_CFGPIO 0x0005d300 /* PBus Ch. 3 PIO config */ -#define HPC_PBUS_CH4_CFGPIO 0x0005d400 /* PBus Ch. 4 PIO config */ -#define HPC_PBUS_CH5_CFGPIO 0x0005d500 /* PBus Ch. 5 PIO config */ -#define HPC_PBUS_CH6_CFGPIO 0x0005d600 /* PBus Ch. 6 PIO config */ -#define HPC_PBUS_CH7_CFGPIO 0x0005d700 /* PBus Ch. 7 PIO config */ -#define HPC_PBUS_CH8_CFGPIO 0x0005d800 /* PBus Ch. 8 PIO config */ -#define HPC_PBUS_CH9_CFGPIO 0x0005d900 /* PBus Ch. 9 PIO config */ -#define HPC_PBUS_CH8_CFGPIO_2 0x0005da00 /* PBus Ch. 8 PIO config */ -#define HPC_PBUS_CH9_CFGPIO_2 0x0005db00 /* PBus Ch. 9 PIO config */ -#define HPC_PBUS_CH8_CFGPIO_3 0x0005dc00 /* PBus Ch. 8 PIO config */ -#define HPC_PBUS_CH9_CFGPIO_3 0x0005dd00 /* PBus Ch. 9 PIO config */ -#define HPC_PBUS_CH8_CFGPIO_4 0x0005de00 /* PBus Ch. 8 PIO config */ -#define HPC_PBUS_CH9_CFGPIO_4 0x0005df00 /* PBus Ch. 9 PIO config */ +#define HPC3_PBUS_CH0_CFGPIO 0x0005d000 /* PBus Ch. 0 PIO config */ +#define HPC3_PBUS_CH1_CFGPIO 0x0005d100 /* PBus Ch. 1 PIO config */ +#define HPC3_PBUS_CH2_CFGPIO 0x0005d200 /* PBus Ch. 2 PIO config */ +#define HPC3_PBUS_CH3_CFGPIO 0x0005d300 /* PBus Ch. 3 PIO config */ +#define HPC3_PBUS_CH4_CFGPIO 0x0005d400 /* PBus Ch. 4 PIO config */ +#define HPC3_PBUS_CH5_CFGPIO 0x0005d500 /* PBus Ch. 5 PIO config */ +#define HPC3_PBUS_CH6_CFGPIO 0x0005d600 /* PBus Ch. 6 PIO config */ +#define HPC3_PBUS_CH7_CFGPIO 0x0005d700 /* PBus Ch. 7 PIO config */ +#define HPC3_PBUS_CH8_CFGPIO 0x0005d800 /* PBus Ch. 8 PIO config */ +#define HPC3_PBUS_CH9_CFGPIO 0x0005d900 /* PBus Ch. 9 PIO config */ +#define HPC3_PBUS_CH8_CFGPIO_2 0x0005da00 /* PBus Ch. 8 PIO config */ +#define HPC3_PBUS_CH9_CFGPIO_2 0x0005db00 /* PBus Ch. 9 PIO config */ +#define HPC3_PBUS_CH8_CFGPIO_3 0x0005dc00 /* PBus Ch. 8 PIO config */ +#define HPC3_PBUS_CH9_CFGPIO_3 0x0005dd00 /* PBus Ch. 9 PIO config */ +#define HPC3_PBUS_CH8_CFGPIO_4 0x0005de00 /* PBus Ch. 8 PIO config */ +#define HPC3_PBUS_CH9_CFGPIO_4 0x0005df00 /* PBus Ch. 9 PIO config */ -#define HPC_PBUS_PROM_WE 0x0005e000 /* PBus boot-prom write +#define HPC3_PBUS_PROM_WE 0x0005e000 /* PBus boot-prom write * enable register */ -#define HPC_PBUS_PROM_SWAP 0x0005e800 /* PBus boot-prom chip-select +#define HPC3_PBUS_PROM_SWAP 0x0005e800 /* PBus boot-prom chip-select * swap register */ -#define HPC_PBUS_GEN_OUT 0x0005f000 /* PBus general-purpose output +#define HPC3_PBUS_GEN_OUT 0x0005f000 /* PBus general-purpose output * register */ -#define HPC_PBUS_BBRAM 0x00060000 /* PBus battery-backed RAM +#define HPC3_PBUS_BBRAM 0x00060000 /* PBus battery-backed RAM * external registers */ diff --git a/sys/arch/sgimips/hpc/if_sq.c b/sys/arch/sgimips/hpc/if_sq.c index 3afd28c1c3fa..0eddb87b10d2 100644 --- a/sys/arch/sgimips/hpc/if_sq.c +++ b/sys/arch/sgimips/hpc/if_sq.c @@ -1,4 +1,4 @@ -/* $NetBSD: if_sq.c,v 1.25 2004/12/30 02:35:42 rumble Exp $ */ +/* $NetBSD: if_sq.c,v 1.26 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -33,7 +33,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.25 2004/12/30 02:35:42 rumble Exp $"); +__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.26 2004/12/30 23:18:09 rumble Exp $"); #include "bpfilter.h" @@ -381,10 +381,11 @@ sq_init(struct ifnet *ifp) /* Set up HPC ethernet DMA config */ if (sc->hpc_regs->revision == 3) { - reg = sq_hpc_read(sc, HPC_ENETR_DMACFG); - sq_hpc_write(sc, HPC_ENETR_DMACFG, reg | ENETR_DMACFG_FIX_RXDC | - ENETR_DMACFG_FIX_INTR | - ENETR_DMACFG_FIX_EOP); + reg = sq_hpc_read(sc, HPC3_ENETR_DMACFG); + sq_hpc_write(sc, HPC3_ENETR_DMACFG, reg | + HPC3_ENETR_DMACFG_FIX_RXDC | + HPC3_ENETR_DMACFG_FIX_INTR | + HPC3_ENETR_DMACFG_FIX_EOP); } /* Pass the start of the receive ring to the HPC */ @@ -625,10 +626,11 @@ sq_start(struct ifnet *ifp) /* Last descriptor gets end-of-packet */ KASSERT(lasttx != -1); if (sc->hpc_regs->revision == 3) - sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= HDD_CTL_EOPACKET; + sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= + HPC3_HDD_CTL_EOPACKET; else sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= - HPC1_HDD_CTL_EOPACKET; + HPC1_HDD_CTL_EOPACKET; SQ_DPRINTF(("%s: transmit %d-%d, len %d\n", sc->sc_dev.dv_xname, sc->sc_nexttx, lasttx, @@ -680,18 +682,18 @@ sq_start(struct ifnet *ifp) * last packet we enqueued, mark it as the last * descriptor. * - * HDD_CTL_INTR will generate an interrupt on - * HPC1 by itself. HPC3 will not interrupt unless - * HDD_CTL_EOPACKET is set as well. + * HPC1_HDD_CTL_INTR will generate an interrupt on + * HPC1. HPC3 requires HPC3_HDD_CTL_EOPACKET in + * addition to HPC3_HDD_CTL_INTR to interrupt. */ KASSERT(lasttx != -1); if (sc->hpc_regs->revision == 3) { - sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= HDD_CTL_INTR | - HDD_CTL_EOCHAIN; + sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= + HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOCHAIN; } else { sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= HPC1_HDD_CTL_INTR; sc->sc_txdesc[lasttx].hpc1_hdd_bufptr |= - HPC1_HDD_CTL_EOCHAIN; + HPC1_HDD_CTL_EOCHAIN; } SQ_CDTXSYNC(sc, lasttx, 1, @@ -714,9 +716,12 @@ sq_start(struct ifnet *ifp) if ((status & sc->hpc_regs->enetx_ctl_active) != 0) { SQ_TRACE(SQ_ADD_TO_DMA, sc, firsttx, status); - /* NB: hpc3_hdd_ctl is also hpc1_hdd_bufptr */ + /* + * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and + * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN + */ sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc3_hdd_ctl &= - ~HDD_CTL_EOCHAIN; + ~HPC3_HDD_CTL_EOCHAIN; if (sc->hpc_regs->revision != 3) sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc1_hdd_ctl @@ -727,11 +732,11 @@ sq_start(struct ifnet *ifp) } else if (sc->hpc_regs->revision == 3) { SQ_TRACE(SQ_START_DMA, sc, firsttx, status); - sq_hpc_write(sc, HPC_ENETX_NDBP, SQ_CDTXADDR(sc, + sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc, firsttx)); /* Kick DMA channel into life */ - sq_hpc_write(sc, HPC_ENETX_CTL, ENETX_CTL_ACTIVE); + sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE); } else { /* * In the HPC1 case where transmit DMA is @@ -900,10 +905,11 @@ sq_rxintr(struct sq_softc *sc) * If this is a CPU-owned buffer, we're at the end of the list. */ if (sc->hpc_regs->revision == 3) - ctl_reg = sc->sc_rxdesc[i].hpc3_hdd_ctl & HDD_CTL_OWN; + ctl_reg = sc->sc_rxdesc[i].hpc3_hdd_ctl & + HPC3_HDD_CTL_OWN; else ctl_reg = sc->sc_rxdesc[i].hpc1_hdd_ctl & - HPC1_HDD_CTL_OWN; + HPC1_HDD_CTL_OWN; if (ctl_reg) { #if defined(SQ_DEBUG) @@ -922,7 +928,7 @@ sq_rxintr(struct sq_softc *sc) framelen = m->m_ext.ext_size - 3; if (sc->hpc_regs->revision == 3) framelen -= - HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl); + HPC3_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl); else framelen -= HPC1_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc1_hdd_ctl); @@ -980,15 +986,18 @@ sq_rxintr(struct sq_softc *sc) /* If anything happened, move ring start/end pointers to new spot */ if (i != sc->sc_nextrx) { - /* NB: hpc3_hdd_ctl is also hpc1_hdd_bufptr */ + /* + * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and + * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN + */ new_end = SQ_PREVRX(i); - sc->sc_rxdesc[new_end].hpc3_hdd_ctl |= HDD_CTL_EOCHAIN; + sc->sc_rxdesc[new_end].hpc3_hdd_ctl |= HPC3_HDD_CTL_EOCHAIN; SQ_CDRXSYNC(sc, new_end, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); orig_end = SQ_PREVRX(sc->sc_nextrx); - sc->sc_rxdesc[orig_end].hpc3_hdd_ctl &= ~HDD_CTL_EOCHAIN; + sc->sc_rxdesc[orig_end].hpc3_hdd_ctl &= ~HPC3_HDD_CTL_EOCHAIN; SQ_CDRXSYNC(sc, orig_end, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); @@ -1165,22 +1174,22 @@ sq_txring_hpc3(struct sq_softc *sc) * the buffer not being finished while the DMA channel * has gone idle. */ - status = sq_hpc_read(sc, HPC_ENETX_CTL); + status = sq_hpc_read(sc, HPC3_ENETX_CTL); SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); /* Check for used descriptor and restart DMA chain if needed */ - if ((sc->sc_txdesc[i].hpc3_hdd_ctl & HDD_CTL_XMITDONE) == 0) { - if ((status & ENETX_CTL_ACTIVE) == 0) { + if (!(sc->sc_txdesc[i].hpc3_hdd_ctl & HPC3_HDD_CTL_XMITDONE)) { + if ((status & HPC3_ENETX_CTL_ACTIVE) == 0) { SQ_TRACE(SQ_RESTART_DMA, sc, i, status); - sq_hpc_write(sc, HPC_ENETX_NDBP, + sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc, i)); /* Kick DMA channel into life */ - sq_hpc_write(sc, HPC_ENETX_CTL, - ENETX_CTL_ACTIVE); + sq_hpc_write(sc, HPC3_ENETX_CTL, + HPC3_ENETX_CTL_ACTIVE); /* * Set a watchdog timer in case the chip diff --git a/sys/arch/sgimips/hpc/sqvar.h b/sys/arch/sgimips/hpc/sqvar.h index 41af0521df66..5e5e82742406 100644 --- a/sys/arch/sgimips/hpc/sqvar.h +++ b/sys/arch/sgimips/hpc/sqvar.h @@ -1,4 +1,4 @@ -/* $NetBSD: sqvar.h,v 1.7 2004/12/29 06:28:14 rumble Exp $ */ +/* $NetBSD: sqvar.h,v 1.8 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 2001 Rafal K. Boni @@ -199,9 +199,9 @@ SQ_INIT_RXDESC(struct sq_softc *sc, unsigned int x) if (sc->hpc_regs->revision == 3) { __rxd->hpc3_hdd_bufptr = (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr; - __rxd->hpc3_hdd_ctl = __m->m_ext.ext_size | HDD_CTL_OWN | - HDD_CTL_INTR | HDD_CTL_EOPACKET | - ((x) == (SQ_NRXDESC - 1) ? HDD_CTL_EOCHAIN : 0); + __rxd->hpc3_hdd_ctl = __m->m_ext.ext_size | HPC3_HDD_CTL_OWN | + HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOPACKET | + ((x) == (SQ_NRXDESC - 1) ? HPC3_HDD_CTL_EOCHAIN : 0); } else { __rxd->hpc1_hdd_bufptr = (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr | ((x) == (SQ_NRXDESC - 1) ? HPC1_HDD_CTL_EOCHAIN : 0); diff --git a/sys/arch/sgimips/sgimips/console.c b/sys/arch/sgimips/sgimips/console.c index babc18b88205..08e19ab3c969 100644 --- a/sys/arch/sgimips/sgimips/console.c +++ b/sys/arch/sgimips/sgimips/console.c @@ -1,4 +1,4 @@ -/* $NetBSD: console.c,v 1.29 2004/12/30 02:41:03 rumble Exp $ */ +/* $NetBSD: console.c,v 1.30 2004/12/30 23:18:09 rumble Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. @@ -28,7 +28,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.29 2004/12/30 02:41:03 rumble Exp $"); +__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.30 2004/12/30 23:18:09 rumble Exp $"); #include "opt_kgdb.h" @@ -145,7 +145,7 @@ gio_video_init(char *consdev) #if (NPCKBC > 0) /* XXX Hardcoded iotag, HPC address XXX */ pckbc_cnattach(1, HPC_BASE_ADDRESS_0 + - HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, KBCMDP, + HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, KBCMDP, PCKBC_KBD_SLOT); #endif break;