diff --git a/sys/arch/evbarm/rpi/rpi2_start.S b/sys/arch/evbarm/rpi/rpi2_start.S
index 83f4bb099007..4b66c65572c5 100644
--- a/sys/arch/evbarm/rpi/rpi2_start.S
+++ b/sys/arch/evbarm/rpi/rpi2_start.S
@@ -38,7 +38,7 @@
 
 #include "assym.h"
 
-RCSID("$NetBSD: rpi2_start.S,v 1.1 2015/02/28 09:34:34 skrll Exp $")
+RCSID("$NetBSD: rpi2_start.S,v 1.2 2015/04/18 11:03:31 skrll Exp $")
 
 #if defined(VERBOSE_INIT_ARM)
 #define	XPUTC(n)	mov r0, n; bl plputc
@@ -117,7 +117,7 @@ _C_LABEL(rpi_start):
 	sub	r8, r8, #KERNEL_BASE_VOFFSET
 #endif
 	bl	arm_boot_l1pt_init
-	XPUTC(#68)
+	XPUTC(#'D')
 
 	/*
 	 * Turn on the MMU, Caches, etc.  Return to new enabled address space.
@@ -142,17 +142,17 @@ _C_LABEL(rpi_start):
 	.pushsection .text,"ax",%progbits
 1:
 #endif
-	XPUTC2(#90)
+	XPUTC2(#'Z')
 
 #if defined(MULTIPROCESSOR)
 	// Now spin up the second processors into the same state we are now.
-	XPUTC2(#77)		// 'M'
-	XPUTC2(#80)		// 'P'
-	XPUTC2(#60)		// '<'
+	XPUTC2(#'M')
+	XPUTC2(#'P')		// 'P'
+	XPUTC2(#'<')		// '<'
 	// Make sure the cache is flushed out to RAM for the other CPUs
 	bl	_C_LABEL(armv7_dcache_wbinv_all)
 
-	XPUTC2(#62)		// '>'
+	XPUTC2(#'>')		// '>'
 #endif /* MULTIPROCESSOR */
 	XPUTC2(#13)
 	XPUTC2(#10)
diff --git a/sys/arch/evbarm/tegra/tegra_start.S b/sys/arch/evbarm/tegra/tegra_start.S
index b025cd4aacdf..45f640ece65e 100644
--- a/sys/arch/evbarm/tegra/tegra_start.S
+++ b/sys/arch/evbarm/tegra/tegra_start.S
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_start.S,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+/* $NetBSD: tegra_start.S,v 1.2 2015/04/18 11:03:31 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014, 2015 The NetBSD Foundation, Inc.
@@ -43,7 +43,7 @@
 #include <arm/nvidia/tegra_reg.h>
 #include <evbarm/tegra/platform.h>  
 
-RCSID("$NetBSD: tegra_start.S,v 1.1 2015/03/29 10:41:59 jmcneill Exp $")
+RCSID("$NetBSD: tegra_start.S,v 1.2 2015/04/18 11:03:31 skrll Exp $")
 
 #if defined(VERBOSE_INIT_ARM)
 #define	XPUTC(n)	mov r0, n; bl xputc
@@ -115,7 +115,7 @@ _C_LABEL(tegra_start):
 	movw	r1, #:lower16:mmu_init_table
 	movt	r1, #:upper16:mmu_init_table
 	bl	arm_boot_l1pt_init
-	XPUTC(#68)
+	XPUTC(#'D')
 
 	/*
 	 * Turn on the MMU, Caches, etc.  Return to new enabled address space.
@@ -139,7 +139,7 @@ _C_LABEL(tegra_start):
 	.pushsection .text,"ax",%progbits
 1:
 #endif
-	XPUTC2(#90)
+	XPUTC2(#'Z')
 
 	/*
 	 * Jump to start in locore.S, which in turn will call initarm and main.