Unroll cache flush/purge ops per 8 cachelines (128bytes).

Improve MI Sonic xfer speed ~2%.
This commit is contained in:
tsutsui 2007-06-08 16:07:49 +00:00
parent f04ca69e5f
commit 7df023a2e5

View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_dma.c,v 1.24 2007/06/07 15:54:09 tsutsui Exp $ */
/* $NetBSD: bus_dma.c,v 1.25 2007/06/08 16:07:49 tsutsui Exp $ */
/*
* This file was taken from from alpha/common/bus_dma.c
@ -46,7 +46,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.24 2007/06/07 15:54:09 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.25 2007/06/08 16:07:49 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -494,9 +494,31 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
e = (pe + CACHELINE_MASK) & ~CACHELINE_MASK;
/* flush cacheline */
while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
DCFL(p);
p += CACHELINE_SIZE;
}
/* flush cachelines per 128bytes */
while ((p < e) && (p & PAGE_MASK) != 0) {
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
}
/* flush page */
@ -505,6 +527,26 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
p += PAGE_SIZE;
}
/* flush cachelines per 128bytes */
while (p + CACHELINE_SIZE * 8 <= e) {
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
DCFL(p);
p += CACHELINE_SIZE;
}
/* flush cacheline */
while (p < e) {
DCFL(p);
@ -530,9 +572,29 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
e = pe & ~CACHELINE_MASK;
/* purge cacheline */
while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
DCPL(p);
p += CACHELINE_SIZE;
}
/* purge cachelines per 128bytes */
while ((p < e) && (p & PAGE_MASK) != 0) {
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
}
/* purge page */
@ -541,6 +603,26 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
p += PAGE_SIZE;
}
/* purge cachelines per 128bytes */
while (p + CACHELINE_SIZE * 8 <= e) {
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
DCPL(p);
p += CACHELINE_SIZE;
}
/* purge cacheline */
while (p < e) {
DCPL(p);