Clean up DMA code. Mask and unmask channels. Warn if terminal count not
reached.
This commit is contained in:
mycroft
parent
29576d7ee9
commit
7dd7c20604
@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
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* $Id: isa.c,v 1.36 1994/02/22 23:39:32 mycroft Exp $
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* $Id: isa.c,v 1.37 1994/03/01 18:16:33 mycroft Exp $
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*/
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/*
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@ -78,6 +78,7 @@ u_short *Crtat = (u_short *)MONO_BUF;
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** Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
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#define DMA1_SR (IO_DMA1 + 1*8) /* status register */
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#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
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#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
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#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
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@ -86,6 +87,7 @@ u_short *Crtat = (u_short *)MONO_BUF;
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** Register definitions for DMA controller 2 (channels 4..7):
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*/
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#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
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#define DMA2_SR (IO_DMA2 + 2*8) /* status register */
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#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
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#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
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#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
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@ -306,10 +308,14 @@ static short dmapageport[8] =
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* external dma control by a board.
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*/
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void
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isa_dmacascade(unsigned chan)
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isa_dmacascade(chan)
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int chan;
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{
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if (chan > 7)
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#ifdef DIAGNOSTIC
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if (chan < 0 || chan > 7)
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panic("isa_dmacascade: impossible request");
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#endif
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0) {
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@ -326,27 +332,33 @@ isa_dmacascade(unsigned chan)
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* problems by using a bounce buffer.
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*/
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void
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isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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{ vm_offset_t phys;
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isa_dmastart(flags, addr, nbytes, chan)
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int flags;
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caddr_t addr;
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vm_size_t nbytes;
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int chan;
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{
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vm_offset_t phys;
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int waport;
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caddr_t newaddr;
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if ( chan > 7
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|| (chan < 4 && nbytes > (1<<16))
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|| (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
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#ifdef DIAGNOSTIC
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if (chan < 0 || chan > 7 ||
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((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) :
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(nbytes >= (1<<16))))
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panic("isa_dmastart: impossible request");
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#endif
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if (isa_dmarangecheck(addr, nbytes, chan)) {
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if (dma_bounce[chan] == 0)
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dma_bounce[chan] =
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/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
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(caddr_t) isaphysmem + NBPG*chan;
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/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
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(caddr_t) isaphysmem + NBPG*chan;
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bounced[chan] = 1;
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newaddr = dma_bounce[chan];
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*(int *) newaddr = 0; /* XXX */
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/* copy bounce buffer on write */
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if (!(flags & B_READ))
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if ((flags & B_READ) == 0)
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bcopy(addr, newaddr, nbytes);
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addr = newaddr;
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}
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@ -361,9 +373,9 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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*/
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/* set dma channel mode, and reset address ff */
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if (flags & B_READ)
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
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outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE);
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else
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
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outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ);
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outb(DMA1_FFC, 0);
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/* send start address */
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@ -377,7 +389,7 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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outb(waport + 1, nbytes>>8);
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/* unmask channel */
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outb(DMA1_SMSK, chan);
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outb(DMA1_SMSK, chan | DMA37SM_CLEAR);
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} else {
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/*
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* Program one of DMA channels 4..7. These are
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@ -385,13 +397,13 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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*/
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/* set dma channel mode, and reset address ff */
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if (flags & B_READ)
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
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outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE);
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else
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
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outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ);
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outb(DMA2_FFC, 0);
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/* send start address */
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waport = DMA2_CHN(chan - 4);
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waport = DMA2_CHN(chan & 3);
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outb(waport, phys>>1);
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outb(waport, phys>>9);
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outb(dmapageport[chan], phys>>16);
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@ -402,20 +414,44 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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outb(waport + 2, nbytes>>8);
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/* unmask channel */
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outb(DMA2_SMSK, chan & 3);
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outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR);
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}
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}
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void
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isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
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isa_dmadone(flags, addr, nbytes, chan)
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int flags;
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caddr_t addr;
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vm_size_t nbytes;
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int chan;
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{
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u_char tc;
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#ifdef DIAGNOSTIC
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if (chan < 0 || chan > 7)
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panic("isa_dmadone: impossible request");
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#endif
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/* check that the terminal count was reached */
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if ((chan & 4) == 0)
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tc = inb(DMA1_SR) & (1 << chan);
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else
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tc = inb(DMA2_SR) & (1 << (chan & 3));
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if (tc == 0)
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/* XXX probably should panic or something */
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log(LOG_ERR, "dma channel %d not finished\n", chan);
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/* copy bounce buffer on read */
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/*if ((flags & (B_PHYS|B_READ)) == (B_PHYS|B_READ))*/
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if (bounced[chan]) {
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bcopy(dma_bounce[chan], addr, nbytes);
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bounced[chan] = 0;
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}
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/* mask channel */
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if ((chan & 4) == 0)
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outb(DMA1_SMSK, DMA37SM_SET | chan);
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else
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outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
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}
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/*
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@ -424,30 +460,32 @@ isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
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* crossing DMA page boundaries).
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* Return true if special handling needed.
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*/
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int
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isa_dmarangecheck(caddr_t va, unsigned length, unsigned chan) {
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isa_dmarangecheck(va, length, chan)
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vm_offset_t va;
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u_long length;
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int chan;
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{
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vm_offset_t phys, priorpage = 0, endva;
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u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
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endva = (vm_offset_t)round_page(va + length);
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for (; va < (caddr_t) endva ; va += NBPG) {
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phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
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#define ISARAM_END RAM_END
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endva = round_page(va + length);
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for (; va < endva ; va += NBPG) {
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phys = trunc_page(pmap_extract(pmap_kernel(), va));
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if (phys == 0)
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panic("isa_dmacheck: no physical page present");
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if (phys > ISARAM_END)
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return (1);
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if (phys >= (1<<24))
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return 1;
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if (priorpage) {
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if (priorpage + NBPG != phys)
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return (1);
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return 1;
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/* check if crossing a DMA page boundary */
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if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
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return (1);
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if ((priorpage ^ phys) & dma_pgmsk)
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return 1;
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}
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priorpage = phys;
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}
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return (0);
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return 0;
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}
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/* head of queue waiting for physmem to become available */
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
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* $Id: isa.c,v 1.36 1994/02/22 23:39:32 mycroft Exp $
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* $Id: isa.c,v 1.37 1994/03/01 18:16:33 mycroft Exp $
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*/
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/*
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@ -78,6 +78,7 @@ u_short *Crtat = (u_short *)MONO_BUF;
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** Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
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#define DMA1_SR (IO_DMA1 + 1*8) /* status register */
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#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
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#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
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#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
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@ -86,6 +87,7 @@ u_short *Crtat = (u_short *)MONO_BUF;
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** Register definitions for DMA controller 2 (channels 4..7):
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*/
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#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
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#define DMA2_SR (IO_DMA2 + 2*8) /* status register */
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#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
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#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
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#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
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@ -306,10 +308,14 @@ static short dmapageport[8] =
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* external dma control by a board.
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*/
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void
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isa_dmacascade(unsigned chan)
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isa_dmacascade(chan)
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int chan;
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{
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if (chan > 7)
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#ifdef DIAGNOSTIC
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if (chan < 0 || chan > 7)
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panic("isa_dmacascade: impossible request");
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#endif
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0) {
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@ -326,27 +332,33 @@ isa_dmacascade(unsigned chan)
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* problems by using a bounce buffer.
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*/
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void
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isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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{ vm_offset_t phys;
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isa_dmastart(flags, addr, nbytes, chan)
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int flags;
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caddr_t addr;
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vm_size_t nbytes;
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int chan;
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{
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vm_offset_t phys;
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int waport;
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caddr_t newaddr;
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if ( chan > 7
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|| (chan < 4 && nbytes > (1<<16))
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|| (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
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#ifdef DIAGNOSTIC
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if (chan < 0 || chan > 7 ||
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((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) :
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(nbytes >= (1<<16))))
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panic("isa_dmastart: impossible request");
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#endif
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if (isa_dmarangecheck(addr, nbytes, chan)) {
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if (dma_bounce[chan] == 0)
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dma_bounce[chan] =
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/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
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(caddr_t) isaphysmem + NBPG*chan;
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/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
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(caddr_t) isaphysmem + NBPG*chan;
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bounced[chan] = 1;
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newaddr = dma_bounce[chan];
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*(int *) newaddr = 0; /* XXX */
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/* copy bounce buffer on write */
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if (!(flags & B_READ))
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if ((flags & B_READ) == 0)
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bcopy(addr, newaddr, nbytes);
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addr = newaddr;
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}
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@ -361,9 +373,9 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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*/
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/* set dma channel mode, and reset address ff */
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if (flags & B_READ)
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
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outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE);
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else
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
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outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ);
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outb(DMA1_FFC, 0);
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/* send start address */
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@ -377,7 +389,7 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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outb(waport + 1, nbytes>>8);
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/* unmask channel */
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outb(DMA1_SMSK, chan);
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outb(DMA1_SMSK, chan | DMA37SM_CLEAR);
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} else {
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/*
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* Program one of DMA channels 4..7. These are
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@ -385,13 +397,13 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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*/
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/* set dma channel mode, and reset address ff */
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if (flags & B_READ)
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
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outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE);
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else
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
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outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ);
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outb(DMA2_FFC, 0);
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/* send start address */
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waport = DMA2_CHN(chan - 4);
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waport = DMA2_CHN(chan & 3);
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outb(waport, phys>>1);
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outb(waport, phys>>9);
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outb(dmapageport[chan], phys>>16);
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@ -402,20 +414,44 @@ isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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outb(waport + 2, nbytes>>8);
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/* unmask channel */
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outb(DMA2_SMSK, chan & 3);
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outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR);
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}
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}
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void
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isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
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isa_dmadone(flags, addr, nbytes, chan)
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int flags;
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caddr_t addr;
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vm_size_t nbytes;
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int chan;
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{
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u_char tc;
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#ifdef DIAGNOSTIC
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if (chan < 0 || chan > 7)
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panic("isa_dmadone: impossible request");
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#endif
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/* check that the terminal count was reached */
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if ((chan & 4) == 0)
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tc = inb(DMA1_SR) & (1 << chan);
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else
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tc = inb(DMA2_SR) & (1 << (chan & 3));
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if (tc == 0)
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/* XXX probably should panic or something */
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log(LOG_ERR, "dma channel %d not finished\n", chan);
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/* copy bounce buffer on read */
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/*if ((flags & (B_PHYS|B_READ)) == (B_PHYS|B_READ))*/
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if (bounced[chan]) {
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bcopy(dma_bounce[chan], addr, nbytes);
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bounced[chan] = 0;
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}
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/* mask channel */
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if ((chan & 4) == 0)
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outb(DMA1_SMSK, DMA37SM_SET | chan);
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else
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outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
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}
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/*
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@ -424,30 +460,32 @@ isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
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* crossing DMA page boundaries).
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* Return true if special handling needed.
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*/
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int
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isa_dmarangecheck(caddr_t va, unsigned length, unsigned chan) {
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isa_dmarangecheck(va, length, chan)
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vm_offset_t va;
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u_long length;
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int chan;
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{
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vm_offset_t phys, priorpage = 0, endva;
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u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
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endva = (vm_offset_t)round_page(va + length);
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for (; va < (caddr_t) endva ; va += NBPG) {
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phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
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#define ISARAM_END RAM_END
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endva = round_page(va + length);
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for (; va < endva ; va += NBPG) {
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phys = trunc_page(pmap_extract(pmap_kernel(), va));
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if (phys == 0)
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panic("isa_dmacheck: no physical page present");
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if (phys > ISARAM_END)
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return (1);
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if (phys >= (1<<24))
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return 1;
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if (priorpage) {
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if (priorpage + NBPG != phys)
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return (1);
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return 1;
|
||||
/* check if crossing a DMA page boundary */
|
||||
if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
|
||||
return (1);
|
||||
if ((priorpage ^ phys) & dma_pgmsk)
|
||||
return 1;
|
||||
}
|
||||
priorpage = phys;
|
||||
}
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* head of queue waiting for physmem to become available */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user