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Use __syncicache() in sljit on powerpc.

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This commit is contained in:
alnsn 2013-11-25 23:53:44 +00:00
parent d501057ddb
commit 7ca7224ef5
2 changed files with 5 additions and 43 deletions
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7
sys/arch/powerpc/include/sljitarch.h
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@ -1,4 +1,4 @@
/* $NetBSD: sljitarch.h,v 1.1 2013/11/17 14:34:12 alnsn Exp $ */
/* $NetBSD: sljitarch.h,v 1.2 2013/11/25 23:53:44 alnsn Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@ -29,6 +29,9 @@
#ifndef _POWERPC_SLJITARCH_H
#define _POWERPC_SLJITARCH_H
#include <sys/types.h>
#include <machine/cpu.h>
#if defined(_LP64)
#define SLJIT_CONFIG_PPC_64 1
#else
@ -36,6 +39,6 @@
#endif
#define SLJIT_CACHE_FLUSH(from, to) \
ppc_cache_flush((from), (to))
__syncicache((from), (to)-(from))
#endif

41
sys/external/bsd/sljit/dist/sljit_src/sljitNativePPC_common.c vendored
View File

@ -37,47 +37,6 @@ typedef sljit_ui sljit_ins;
#include <sys/cache.h>
#endif
static void ppc_cache_flush(sljit_ins *from, sljit_ins *to)
{
#ifdef _AIX
_sync_cache_range((caddr_t)from, (int)((size_t)to - (size_t)from));
#elif defined(__GNUC__) || (defined(__IBM_GCC_ASM) && __IBM_GCC_ASM)
# if defined(_ARCH_PWR) || defined(_ARCH_PWR2)
/* Cache flush for POWER architecture. */
while (from < to) {
__asm__ volatile (
"clf 0, %0\n"
"dcs\n"
: : "r"(from)
);
from++;
}
__asm__ volatile ( "ics" );
# elif defined(_ARCH_COM) && !defined(_ARCH_PPC)
# error "Cache flush is not implemented for PowerPC/POWER common mode."
# else
/* Cache flush for PowerPC architecture. */
while (from < to) {
__asm__ volatile (
"dcbf 0, %0\n"
"sync\n"
"icbi 0, %0\n"
: : "r"(from)
);
from++;
}
__asm__ volatile ( "isync" );
# endif
# ifdef __xlc__
# warning "This file may fail to compile if -qfuncsect is used"
# endif
#elif defined(__xlc__)
#error "Please enable GCC syntax for inline assembly statements with -qasm=gcc"
#else
#error "This platform requires a cache flush implementation."
#endif /* _AIX */
}
#define TMP_REG1 (SLJIT_NO_REGISTERS + 1)
#define TMP_REG2 (SLJIT_NO_REGISTERS + 2)
#define TMP_REG3 (SLJIT_NO_REGISTERS + 3)