Pull up the following, requested by msaitoh in ticket #629:
sys/dev/pci/pcireg.h 1.148 sys/dev/pci/pci_subr.c 1.218-1.219 - Fix a bug that the virtual channel extended configuration's arbitration phase register can't be decoded correctly. - Fix typo.
This commit is contained in:
martin
parent
eeb9f0d030
commit
7c9b24a10d
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.215.2.1 2019/09/26 18:52:57 martin Exp $ */
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/* $NetBSD: pci_subr.c,v 1.215.2.2 2020/01/21 15:15:23 martin Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.1 2019/09/26 18:52:57 martin Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.2 2020/01/21 15:15:23 martin Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -2864,36 +2864,42 @@ pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff)
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}
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}
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/*
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* Helper function to print the arbitration phase register.
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*
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* phases: Number of phases in the arbitration tables.
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* arbsize: Number of bits in each phase.
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* indent: Add more two spaces if it's true.
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*/
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static void
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pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
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pcireg_t parbsel, int parbsize)
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const int phases, int arbsize, bool indent)
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{
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pcireg_t reg;
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int num = 16 << parbsel;
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int num_per_reg = sizeof(pcireg_t) / parbsize;
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int num_per_reg = 32 / arbsize;
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int i, j;
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/* First, dump the table */
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for (i = 0; i < num; i += num_per_reg) {
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reg = regs[o2i(off + i / num_per_reg)];
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printf(" %s Arbitration Table: 0x%08x\n", name, reg);
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}
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/* And then, decode each entry */
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for (i = 0; i < num; i += num_per_reg) {
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reg = regs[o2i(off + i / num_per_reg)];
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for (j = 0; j < num_per_reg; j++)
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printf(" Phase[%d]: %d\n", j, reg);
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printf("%s %s Arbitration Table:\n", indent ? " " : "", name);
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for (i = 0; i < phases; i += num_per_reg) {
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reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))];
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for (j = 0; j < num_per_reg; j++) {
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printf("%s Phase[%d]: 0x%x\n", indent ? " " : "",
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i + j,
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(uint32_t)(reg & __BITS(arbsize - 1, 0)));
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reg >>= arbsize;
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}
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}
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}
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/* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */
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static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 };
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static void
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pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
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{
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pcireg_t reg, n;
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int parbtab, parbsize;
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pcireg_t parbsel;
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int varbtab, varbsize;
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pcireg_t varbsel;
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int arbtab, parbsize;
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pcireg_t arbsel;
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int i, count;
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printf("\n Virtual Channel Register\n");
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@ -2919,19 +2925,23 @@ pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
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reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
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onoff("WRR arbitration with 128 phases",
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reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
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varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
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printf(" VC Arbitration Table Offset: 0x%x\n", varbtab);
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arbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
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printf(" VC Arbitration Table Offset: 0x%x\n", arbtab);
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reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
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printf(" Port VC Control register: 0x%04x\n", reg);
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varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
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printf(" VC Arbitration Select: 0x%x\n", varbsel);
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arbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
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printf(" VC Arbitration Select: 0x%x\n", arbsel);
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reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
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printf(" Port VC Status register: 0x%04x\n", reg);
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onoff("VC Arbitration Table Status",
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reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
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if ((arbtab != 0) && (arbsel != 0))
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pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16),
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"VC", arb_phases[arbsel], 4, false);
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for (i = 0; i < count + 1; i++) {
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reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
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printf(" VC number %d\n", i);
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@ -2954,9 +2964,10 @@ pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
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reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
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n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
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printf(" Maximum Time Slots: %d\n", n);
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parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
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arbtab = __SHIFTOUT(reg,
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PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET);
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printf(" Port Arbitration Table offset: 0x%02x\n",
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parbtab);
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arbtab);
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reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
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printf(" VC Resource Control Register: 0x%08x\n", reg);
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@ -2967,8 +2978,8 @@ pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
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* the Port Arbitration logic and it's always 0 on read, so
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* we don't print it.
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*/
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parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
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printf(" Port Arbitration Select: 0x%x\n", parbsel);
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arbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
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printf(" Port Arbitration Select: 0x%x\n", arbsel);
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n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
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printf(" VC ID: %d\n", n);
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onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
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@ -2980,15 +2991,11 @@ pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
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onoff(" VC Negotiation Pending",
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reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
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if ((parbtab != 0) && (parbsel != 0))
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pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
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"Port", parbsel, parbsize);
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if ((arbtab != 0) && (arbsel != 0))
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pci_conf_print_vc_cap_arbtab(regs,
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extcapoff + (arbtab * 16),
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"Port", arb_phases[arbsel], parbsize, true);
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}
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varbsize = 8;
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if ((varbtab != 0) && (varbsel != 0))
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pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
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" VC", varbsel, varbsize);
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}
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/*
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@ -3531,7 +3538,7 @@ pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff)
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ctl = reg & 0xffff;
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sta = reg >> 16;
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printf(" Control Register: 0x%04x\n", ctl);
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onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E);
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onoff("Enable", reg, PCI_PAGE_REQ_CTL_E);
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onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
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printf(" Status Register: 0x%04x\n", sta);
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@ -1,4 +1,4 @@
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/* $NetBSD: pcireg.h,v 1.147 2019/03/01 09:26:00 msaitoh Exp $ */
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/* $NetBSD: pcireg.h,v 1.147.4.1 2020/01/21 15:15:23 martin Exp $ */
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/*
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* Copyright (c) 1995, 1996, 1999, 2000
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@ -1886,7 +1886,7 @@ struct pci_rom {
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* Page Request
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*/
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#define PCI_PAGE_REQ_CTL 0x04 /* Control Register */
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#define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enalbe */
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#define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enable */
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#define PCI_PAGE_REQ_CTL_R __BIT(1) /* Reset */
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#define PCI_PAGE_REQ_STA 0x04 /* Status Register */
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#define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */
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