rk_gmac: clean up code for setting up clock delay lines a bit
- break long lines - move toggle to enable it under a single #ifdef notyet I've tested it and it works, but I'm keeping the #ifdef notyet for now because it didn't solve the original problem I was debugging.
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tnn
parent
636ecf90f7
commit
7bd92a1a3d
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@ -1,4 +1,4 @@
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/* $NetBSD: rk_gmac.c,v 1.14 2019/07/21 08:24:32 mrg Exp $ */
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/* $NetBSD: rk_gmac.c,v 1.15 2019/11/09 17:21:48 tnn Exp $ */
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/*-
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* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
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@ -28,7 +28,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.14 2019/07/21 08:24:32 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.15 2019/11/09 17:21:48 tnn Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -90,7 +90,7 @@ struct rk_gmac_softc {
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#define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0)
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static void
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rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay)
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rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay, bool set_delay)
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{
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struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc;
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uint32_t write_mask, write_val;
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@ -98,19 +98,30 @@ rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_d
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syscon_lock(rk_sc->sc_syscon);
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write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16;
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write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL);
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syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val);
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write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII,
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RK3328_GRF_MAC_CON1_SEL);
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syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1,
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write_mask | write_val);
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#if notyet
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write_mask = (RK3328_GRF_MAC_CON0_TXDLY | RK3328_GRF_MAC_CON0_RXDLY) << 16;
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write_val = __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) |
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if (set_delay) {
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write_mask = (
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RK3328_GRF_MAC_CON0_TXDLY |
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RK3328_GRF_MAC_CON0_RXDLY) << 16;
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write_val =
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__SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) |
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__SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY);
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syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, write_mask | write_val);
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syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0,
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write_mask | write_val);
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write_mask = (RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16;
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write_val = RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN;
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syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val);
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#endif
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write_mask = (
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RK3328_GRF_MAC_CON1_RXDLY_EN |
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RK3328_GRF_MAC_CON1_TXDLY_EN) << 16;
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write_val =
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RK3328_GRF_MAC_CON1_RXDLY_EN |
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RK3328_GRF_MAC_CON1_TXDLY_EN;
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syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1,
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write_mask | write_val);
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}
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syscon_unlock(rk_sc->sc_syscon);
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}
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@ -163,32 +174,34 @@ rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed)
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#define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0)
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static void
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rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay)
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rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay,
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u_int rx_delay, bool set_delay)
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{
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struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc;
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const uint32_t con5_mask =
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(RK3399_GRF_SOC_CON5_RMII_MODE | RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16;
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const uint32_t con5 = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL);
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#if notyet
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const uint32_t con6_mask =
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(RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA |
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RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA |
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RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG |
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RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16;
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const uint32_t con6 =
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(tx_delay ? RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA : 0) |
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(rx_delay ? RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA : 0) |
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__SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) |
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__SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG);
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#endif
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uint32_t write_mask, write_val;
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syscon_lock(rk_sc->sc_syscon);
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syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask);
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#if notyet
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syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6, con6 | con6_mask);
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#endif
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write_mask = (
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RK3399_GRF_SOC_CON5_RMII_MODE |
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RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16;
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write_val = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL);
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syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5,
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write_mask | write_val);
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if (set_delay) {
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write_mask = (
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RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA |
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RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA |
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RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG |
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RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16;
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write_val =
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(tx_delay ? RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA : 0) |
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(rx_delay ? RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA : 0) |
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__SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) |
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__SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG);
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syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6,
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write_mask | write_val);
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}
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syscon_unlock(rk_sc->sc_syscon);
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}
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@ -339,6 +352,11 @@ rk_gmac_attach(device_t parent, device_t self, void *aux)
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bus_addr_t addr;
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bus_size_t size;
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u_int tx_delay, rx_delay;
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#ifdef notyet
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bool set_delay = true;
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#else
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bool set_delay = false;
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#endif
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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@ -353,11 +371,15 @@ rk_gmac_attach(device_t parent, device_t self, void *aux)
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return;
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}
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if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0)
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if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) {
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tx_delay = RK_GMAC_TXDLY_DEFAULT;
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set_delay = false;
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}
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if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0)
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if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) {
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rx_delay = RK_GMAC_RXDLY_DEFAULT;
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set_delay = false;
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}
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sc->sc_dev = self;
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sc->sc_bst = faa->faa_bst;
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@ -395,7 +417,8 @@ rk_gmac_attach(device_t parent, device_t self, void *aux)
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switch (rk_sc->sc_type) {
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case GMAC_RK3328:
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if (strcmp(phy_mode, "rgmii") == 0) {
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rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay);
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rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay,
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set_delay);
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sc->sc_set_speed = rk3328_gmac_set_speed_rgmii;
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} else {
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@ -405,7 +428,8 @@ rk_gmac_attach(device_t parent, device_t self, void *aux)
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break;
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case GMAC_RK3399:
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if (strcmp(phy_mode, "rgmii") == 0) {
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rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay);
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rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay,
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set_delay);
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sc->sc_set_speed = rk3399_gmac_set_speed_rgmii;
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} else {
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