From 7bc4024944e11bfebef76645764ab8c80a65f9c1 Mon Sep 17 00:00:00 2001
From: tsutsui <tsutsui@NetBSD.org>
Date: Wed, 11 Dec 2019 16:16:13 +0000
Subject: [PATCH] Fix a longstanding "freeze right after enabling interrupt"
 problem.

With this fix, finally NetBSD/emips on Giano is fully functional.
See PR/45080 for more details.

Should be pulled up to netbsd-9.
---
 sys/arch/emips/emips/interrupt.c | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/sys/arch/emips/emips/interrupt.c b/sys/arch/emips/emips/interrupt.c
index ab93e3515335..a82434c20b3e 100644
--- a/sys/arch/emips/emips/interrupt.c
+++ b/sys/arch/emips/emips/interrupt.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: interrupt.c,v 1.7 2019/12/09 16:19:11 tsutsui Exp $	*/
+/*	$NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $	*/
 
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2019/12/09 16:19:11 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -102,6 +102,19 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t status)
 
 	curcpu()->ci_data.cpu_nintr++;
 
+#if 0
+	/*
+	 * According to Giano simulator sources (Cpus/mips_cpu.cpp),
+	 * interrupt register bits in CAUSE register are updated
+	 * only when the exception is triggered. This means checking
+	 * CAUSE register via splintr() in a while loop in this
+	 * interrupt handler doesn't work as expected on Giano.
+	 *
+	 * I don't know whether the real FPGA eMIPS has the same
+	 * design as the Giano simulator, but for now I'd like to
+	 * choose 'call only one handler per each interrupt' strategy,
+	 * as the original NetBSD/emips implementation.
+	 */
 	while (ppl < (ipl = splintr(&ipending))) {
 		splx(ipl);
 		/* device interrupts */
@@ -110,6 +123,14 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t status)
 		}
 		(void)splhigh();
 	}
+#else
+	ipl = splintr(&ipending);
+	__USE(ipl);
+	/* device interrupts */
+	if (ipending & MIPS_INT_MASK_5) {
+		(*platform.iointr)(status, pc, ipending);
+	}
+#endif
 }
 
 /*