Add MI NCR/Symbios 53c700 SCSI driver.
This "oosiop" driver was originally written by Shuichiro URATA for arc port, and then it was modified by me to make it work also on hp700. This driver has been tested on my NEC Express5800/240 with 53c700-66 for several months, and also tested on HP9000 735/125 with 53c700 (though current hp700 port has been broken since SA merge). Both sync transfer and disconnect/reselect work fine, but tagged queuing is not implemented yet.
This commit is contained in:
tsutsui
parent
dcd13397db
commit
7b4697bdbe
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@ -1,4 +1,4 @@
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# $NetBSD: files,v 1.604 2003/03/16 11:50:27 jdolecek Exp $
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# $NetBSD: files,v 1.605 2003/04/06 09:48:41 tsutsui Exp $
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# @(#)files.newconf 7.5 (Berkeley) 5/10/93
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@ -385,6 +385,10 @@ device lfmport: scsi
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attach lfmport at lfmiop
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file dev/ic/lfmiop.c lfmiop
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# Symbios/NCR 53c700 SCSI controllers
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device oosiop: scsi
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file dev/ic/oosiop.c oosiop
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# Symbios/NCR 53c710 SCSI controllers
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#
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device osiop: scsi
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,327 @@
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/* $NetBSD: oosiopreg.h,v 1.1 2003/04/06 09:48:43 tsutsui Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)siopreg.h 7.3 (Berkeley) 2/5/91
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*/
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/*
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* NCR 53C700 SCSI interface hardware description.
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*
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* From the Mach scsi driver for the 53C700 and amiga siop driver
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*/
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#define OOSIOP_SCNTL0 0x00 /* rw: SCSI control reg 0 */
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#define OOSIOP_SCNTL1 0x01 /* rw: SCSI control reg 1 */
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#define OOSIOP_SDID 0x02 /* rw: SCSI destination ID */
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#define OOSIOP_SIEN 0x03 /* rw: SCSI interrupt enable */
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#define OOSIOP_SCID 0x04 /* rw: SCSI Chip ID reg */
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#define OOSIOP_SXFER 0x05 /* rw: SCSI Transfer reg */
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#define OOSIOP_SODL 0x06 /* rw: SCSI Output Data Latch */
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#define OOSIOP_SOCL 0x07 /* rw: SCSI Output Control Latch */
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#define OOSIOP_SFBR 0x08 /* ro: SCSI First Byte Received */
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#define OOSIOP_SIDL 0x09 /* ro: SCSI Input Data Latch */
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#define OOSIOP_SBDL 0x0a /* ro: SCSI Bus Data Lines */
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#define OOSIOP_SBCL 0x0b /* rw: SCSI Bus Control Lines */
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#define OOSIOP_DSTAT 0x0c /* ro: DMA status */
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#define OOSIOP_SSTAT0 0x0d /* ro: SCSI status reg 0 */
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#define OOSIOP_SSTAT1 0x0e /* ro: SCSI status reg 1 */
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#define OOSIOP_SSTAT2 0x0f /* ro: SCSI status reg 2 */
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#define OOSIOP_SCRA0 0x10 /* rw: Scratch A */
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#define OOSIOP_SCRA1 0x11
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#define OOSIOP_SCRA2 0x12
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#define OOSIOP_SCRA3 0x13
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#define OOSIOP_CTEST0 0x14 /* ro: Chip test register 0 */
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#define OOSIOP_CTEST1 0x15 /* ro: Chip test register 1 */
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#define OOSIOP_CTEST2 0x16 /* ro: Chip test register 2 */
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#define OOSIOP_CTEST3 0x17 /* ro: Chip test register 3 */
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#define OOSIOP_CTEST4 0x18 /* rw: Chip test register 4 */
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#define OOSIOP_CTEST5 0x19 /* rw: Chip test register 5 */
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#define OOSIOP_CTEST6 0x1a /* rw: Chip test register 6 */
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#define OOSIOP_CTEST7 0x1b /* rw: Chip test register 7 */
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#define OOSIOP_TEMP 0x1c /* rw: Temporary Stack reg */
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#define OOSIOP_DFIFO 0x20 /* rw: DMA FIFO */
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#define OOSIOP_ISTAT 0x21 /* rw: Interrupt Status reg */
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#define OOSIOP_CTEST8 0x22 /* rw: Chip test register 8 */
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#define OOSIOP_CTEST9 0x23 /* ro: Chip test register 9 */
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#define OOSIOP_DBC 0x24 /* rw: DMA Byte Counter reg */
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#define OOSIOP_DCMD 0x27 /* rw: DMA Command Register */
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#define OOSIOP_DNAD 0x28 /* rw: DMA Next Address */
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#define OOSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */
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#define OOSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */
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#define OOSIOP_DMODE 0x34 /* rw: DMA Mode reg */
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#define OOSIOP_RES35 0x35
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#define OOSIOP_RES36 0x36
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#define OOSIOP_RES37 0x37
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#define OOSIOP_RES38 0x38
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#define OOSIOP_DIEN 0x39 /* rw: DMA Interrupt Enable */
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#define OOSIOP_DWT 0x3a /* rw: DMA Watchdog Timer */
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#define OOSIOP_DCNTL 0x3b /* rw: DMA Control reg */
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#define OOSIOP_SCRB0 0x3c /* rw: Scratch B */
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#define OOSIOP_SCRB1 0x3d
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#define OOSIOP_SCRB2 0x3e
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#define OOSIOP_SCRB3 0x3f
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#define OOSIOP_NREGS 0x40
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/*
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* Register defines
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*/
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/* Scsi control register 0 (scntl0) */
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#define OOSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */
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#define OOSIOP_ARB_SIMPLE 0x00
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#define OOSIOP_ARB_FULL 0xc0
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#define OOSIOP_SCNTL0_START 0x20 /* Start Sequence */
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#define OOSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */
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#define OOSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */
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#define OOSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */
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#define OOSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */
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#define OOSIOP_SCNTL0_TRG 0x01 /* Target Mode */
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/* Scsi control register 1 (scntl1) */
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#define OOSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */
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#define OOSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */
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#define OOSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */
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#define OOSIOP_SCNTL1_CON 0x10 /* Connected */
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#define OOSIOP_SCNTL1_RST 0x08 /* Assert RST */
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#define OOSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */
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#define OOSIOP_SCNTL1_SND 0x02 /* Start Send operation */
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#define OOSIOP_SCNTL1_RCV 0x01 /* Start Receive operation */
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/* Scsi interrupt enable register (sien) */
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#define OOSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */
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#define OOSIOP_SIEN_FC 0x40 /* Function Complete */
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#define OOSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */
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#define OOSIOP_SIEN_SEL 0x10 /* (Re)Selected */
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#define OOSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */
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#define OOSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */
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#define OOSIOP_SIEN_RST 0x02 /* RST asserted */
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#define OOSIOP_SIEN_PAR 0x01 /* Parity Error */
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/* Scsi chip ID (scid) */
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#define OOSIOP_SCID_VALUE(i) (1 << i)
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/* Scsi transfer register (sxfer) */
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#define OOSIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/
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ATN asserted */
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#define OOSIOP_SXFER_TP 0x70 /* Synch Transfer Period */
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/* see specs for formulas:
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Period = TCP * (4 + XFERP )
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TCP = 1 + CLK + 1..2;
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*/
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#define OOSIOP_SXFER_MO 0x0f /* Synch Max Offset */
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#define OOSIOP_MAX_OFFSET 8
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/* Scsi output data latch register (sodl) */
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/* Scsi output control latch register (socl) */
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#define OOSIOP_REQ 0x80 /* SCSI signal <x> asserted */
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#define OOSIOP_ACK 0x40
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#define OOSIOP_BSY 0x20
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#define OOSIOP_SEL 0x10
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#define OOSIOP_ATN 0x08
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#define OOSIOP_MSG 0x04
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#define OOSIOP_CD 0x02
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#define OOSIOP_IO 0x01
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#define OOSIOP_PHASE(socl) SCSI_PHASE(socl)
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/* Scsi first byte received register (sfbr) */
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/* Scsi input data latch register (sidl) */
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/* Scsi bus data lines register (sbdl) */
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/* Scsi bus control lines register (sbcl). Same as socl */
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#define OOSIOP_SBCL_SSCF1 0x02 /* wo */
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#define OOSIOP_SBCL_SSCF0 0x01 /* wo */
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/* DMA status register (dstat) */
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#define OOSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */
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#define OOSIOP_DSTAT_ABRT 0x10 /* Aborted */
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#define OOSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */
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#define OOSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */
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#define OOSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */
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#define OOSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */
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/* Scsi status register 0 (sstat0) */
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#define OOSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */
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#define OOSIOP_SSTAT0_FC 0x40 /* Function Complete */
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#define OOSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */
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#define OOSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */
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#define OOSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */
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#define OOSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */
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#define OOSIOP_SSTAT0_RST 0x02 /* RST asserted */
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#define OOSIOP_SSTAT0_PAR 0x01 /* Parity Error */
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/* Scsi status register 1 (sstat1) */
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#define OOSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */
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#define OOSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */
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#define OOSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */
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#define OOSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */
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#define OOSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */
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#define OOSIOP_SSTAT1_WOA 0x04 /* Won arbitration */
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#define OOSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */
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#define OOSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */
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/* Scsi status register 2 (sstat2) */
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#define OOSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */
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#define OOSIOP_SCSI_FIFO_DEEP 8
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#define OOSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */
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#define OOSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */
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#define OOSIOP_SSTAT2_CD 0x02
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#define OOSIOP_SSTAT2_IO 0x01
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/* Chip test register 0 (ctest0) */
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#define OOSIOP_CTEST0_RTRG 0x02 /* Real Target Mode */
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#define OOSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */
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/* Chip test register 1 (ctest1) */
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#define OOSIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom
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(high->byte3) */
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#define OOSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */
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/* Chip test register 2 (ctest2) */
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#define OOSIOP_CTEST2_SOFF 0x20 /* Synch Offset compare
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(1-> zero Init, max Tgt) */
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#define OOSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */
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#define OOSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */
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#define OOSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */
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#define OOSIOP_CTEST2_DREQ 0x02 /* DREQ status */
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#define OOSIOP_CTEST2_DACK 0x01 /* DACK status */
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/* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
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/* Chip test register 4 (ctest4) */
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#define OOSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */
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#define OOSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */
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#define OOSIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */
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#define OOSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */
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#define OOSIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select
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(from ctest6) 4->0, .. 7->3 */
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/* Chip test register 5 (ctest5) */
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#define OOSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */
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#define OOSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */
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#define OOSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */
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#define OOSIOP_CTEST5_MASR 0x10 /* Master set/reset pulses
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(of bits 3-0) */
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#define OOSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */
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#define OOSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */
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#define OOSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */
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#define OOSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */
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/* Chip test register 6 (ctest6) DMA FIFO access */
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/* Chip test register 7 (ctest7) */
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#define OOSIOP_CTEST7_STD 0x10 /* Selection timeout disable */
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#define OOSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */
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#define OOSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */
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#define OOSIOP_CTEST7_DIFF 0x01 /* Differential mode */
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/* DMA FIFO register (dfifo) */
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#define OOSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */
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#define OOSIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */
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#define OOSIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */
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/* Interrupt status register (istat) */
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#define OOSIOP_ISTAT_ABRT 0x80 /* Abort operation */
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#define OOSIOP_ISTAT_CON 0x08 /* Connected */
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#define OOSIOP_ISTAT_PRE 0x04 /* Pointer register empty */
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#define OOSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */
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#define OOSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */
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/* Chip test register 8 (ctest8) */
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/* DMA Byte Counter register (dbc) */
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#define OOSIOP_DBC_MAX 0x00ffffff
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/* DMA Mode register (dmode) */
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#define OOSIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */
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#define OOSIOP_DMODE_BL_1 0x00
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#define OOSIOP_DMODE_BL_2 0x40
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#define OOSIOP_DMODE_BL_4 0x80
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#define OOSIOP_DMODE_BL_8 0xc0
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#define OOSIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */
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#define OOSIOP_DMODE_286 0x10 /* 286 mode */
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#define OOSIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */
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#define OOSIOP_DMODE_FAM 0x04 /* fixed address mode */
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#define OOSIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */
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#define OOSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */
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/* DMA interrupt enable register (dien) */
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#define OOSIOP_DIEN_BF 0x20 /* On Bus Fault */
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#define OOSIOP_DIEN_ABRT 0x10 /* On Abort */
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#define OOSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */
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#define OOSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */
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#define OOSIOP_DIEN_WTD 0x02 /* On watchdog timeout */
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#define OOSIOP_DIEN_IID 0x01 /* On illegal instruction detected */
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/* DMA control register (dcntl) */
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#define OOSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */
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#define OOSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 MHz, div=2 */
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#define OOSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 MHz, div=1.5 */
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#define OOSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 MHz, div=1 */
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#define OOSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 MHz, div=3 */
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#define OOSIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */
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#define OOSIOP_DCNTL_SSM 0x10 /* Single step mode */
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#define OOSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */
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#define OOSIOP_DCNTL_STD 0x04 /* Start DMA operation */
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#define OOSIOP_DCNTL_RST 0x01 /* Software reset */
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@ -0,0 +1,157 @@
|
|||
/* $NetBSD: oosiopvar.h,v 1.1 2003/04/06 09:48:43 tsutsui Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Shuichiro URATA. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define OOSIOP_NTGT 8 /* Max targets */
|
||||
#define OOSIOP_NCB 32 /* Initial command buffers */
|
||||
#define OOSIOP_NSG (MIN(btoc(MAXPHYS) + 1, 32)) /* Max S/G operation */
|
||||
#define OOSIOP_MAX_XFER ctob(OOSIOP_NSG - 1)
|
||||
|
||||
struct oosiop_xfer {
|
||||
/* script for scatter/gather DMA (move*nsg+jump) */
|
||||
u_int32_t datain_scr[(OOSIOP_NSG + 1) * 2];
|
||||
u_int32_t dataout_scr[(OOSIOP_NSG + 1) * 2];
|
||||
|
||||
u_int8_t msgin[8];
|
||||
u_int8_t msgout[8];
|
||||
u_int8_t status;
|
||||
u_int8_t pad[7];
|
||||
} __attribute__((__packed__));
|
||||
|
||||
#define SCSI_OOSIOP_NOSTATUS 0xff /* device didn't report status */
|
||||
|
||||
#define OOSIOP_XFEROFF(x) offsetof(struct oosiop_xfer, x)
|
||||
#define OOSIOP_DINSCROFF OOSIOP_XFEROFF(datain_scr[0])
|
||||
#define OOSIOP_DOUTSCROFF OOSIOP_XFEROFF(dataout_scr[0])
|
||||
#define OOSIOP_MSGINOFF OOSIOP_XFEROFF(msgin[0])
|
||||
#define OOSIOP_MSGOUTOFF OOSIOP_XFEROFF(msgout[0])
|
||||
|
||||
#define OOSIOP_XFERSCR_SYNC(sc, cb, ops) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (cb)->xferdma, OOSIOP_DINSCROFF, \
|
||||
OOSIOP_MSGINOFF - OOSIOP_DINSCROFF, (ops))
|
||||
#define OOSIOP_DINSCR_SYNC(sc, cb, ops) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (cb)->xferdma, OOSIOP_DINSCROFF, \
|
||||
OOSIOP_DOUTSCROFF - OOSIOP_DINSCROFF, (ops))
|
||||
#define OOSIOP_DOUTSCR_SYNC(sc, cb, ops) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (cb)->xferdma, OOSIOP_DOUTSCROFF,\
|
||||
OOSIOP_MSGINOFF - OOSIOP_DOUTSCROFF, (ops))
|
||||
#define OOSIOP_XFERMSG_SYNC(sc, cb, ops) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (cb)->xferdma, OOSIOP_MSGINOFF, \
|
||||
sizeof(struct oosiop_xfer) - OOSIOP_MSGINOFF, (ops))
|
||||
|
||||
#define OOSIOP_SCRIPT_SYNC(sc, ops) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_scrdma, \
|
||||
0, sizeof(oosiop_script), (ops))
|
||||
|
||||
struct oosiop_cb {
|
||||
TAILQ_ENTRY(oosiop_cb) chain;
|
||||
|
||||
struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */
|
||||
int flags;
|
||||
int id; /* target scsi id */
|
||||
int lun; /* target lun */
|
||||
|
||||
bus_dmamap_t cmddma; /* DMA map for command out */
|
||||
bus_dmamap_t datadma; /* DMA map for data I/O */
|
||||
bus_dmamap_t xferdma; /* DMA map for xfer block */
|
||||
|
||||
int curdp; /* current data pointer */
|
||||
int savedp; /* saved data pointer */
|
||||
int msgoutlen;
|
||||
|
||||
struct oosiop_xfer *xfer; /* DMA xfer block */
|
||||
};
|
||||
|
||||
/* oosiop_cb flags */
|
||||
#define CBF_SELTOUT 0x01 /* Selection timeout */
|
||||
#define CBF_TIMEOUT 0x02 /* Command timeout */
|
||||
|
||||
TAILQ_HEAD(oosiop_cb_queue, oosiop_cb);
|
||||
|
||||
struct oosiop_target {
|
||||
struct oosiop_cb *nexus;
|
||||
int flags;
|
||||
u_int8_t scf; /* synchronous clock divisor */
|
||||
u_int8_t sxfer; /* synchronous period and offset */
|
||||
};
|
||||
|
||||
/* target flags */
|
||||
#define TGTF_SYNCNEG 0x01 /* Trigger synchronous negotiation */
|
||||
#define TGTF_WAITSDTR 0x02 /* Waiting SDTR from target */
|
||||
|
||||
struct oosiop_softc {
|
||||
struct device sc_dev;
|
||||
|
||||
bus_space_tag_t sc_bst; /* bus space tag */
|
||||
bus_space_handle_t sc_bsh; /* bus space handle */
|
||||
|
||||
bus_dma_tag_t sc_dmat; /* bus dma tag */
|
||||
bus_dmamap_t sc_scrdma; /* script dma map */
|
||||
|
||||
bus_addr_t sc_scrbase; /* script dma base address */
|
||||
u_int32_t *sc_scr; /* ptr to script memory */
|
||||
|
||||
int sc_chip; /* 700 or 700-66 */
|
||||
#define OOSIOP_700 0
|
||||
#define OOSIOP_700_66 1
|
||||
|
||||
int sc_id; /* SCSI ID of this interface */
|
||||
int sc_freq; /* SCLK frequency */
|
||||
int sc_ccf; /* asynchronous divisor (*10) */
|
||||
u_int8_t sc_dcntl;
|
||||
u_int8_t sc_minperiod;
|
||||
|
||||
struct oosiop_target sc_tgt[OOSIOP_NTGT];
|
||||
|
||||
struct scsipi_adapter sc_adapter;
|
||||
struct scsipi_channel sc_channel;
|
||||
|
||||
/* Lists of command blocks */
|
||||
struct oosiop_cb_queue sc_free_cb;
|
||||
struct oosiop_cb_queue sc_cbq; /* command issue queue */
|
||||
struct oosiop_cb *sc_curcb; /* current command */
|
||||
struct oosiop_cb *sc_lastcb; /* last activated command */
|
||||
|
||||
bus_addr_t sc_reselbuf; /* msgin buffer for reselection */
|
||||
int sc_resid; /* reselected target id */
|
||||
|
||||
int sc_active;
|
||||
int sc_nextdsp;
|
||||
};
|
||||
|
||||
#define oosiop_read_1(sc, addr) \
|
||||
bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (addr))
|
||||
#define oosiop_write_1(sc, addr, data) \
|
||||
bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (addr), (data))
|
||||
/* XXX byte swapping should be handled by MD bus_space(9)? */
|
||||
#define oosiop_read_4(sc, addr) \
|
||||
le32toh(bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (addr)))
|
||||
#define oosiop_write_4(sc, addr, data) \
|
||||
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (addr), htole32(data))
|
||||
|
||||
void oosiop_attach(struct oosiop_softc *);
|
||||
int oosiop_intr(struct oosiop_softc *);
|
||||
|
|
@ -1,9 +1,7 @@
|
|||
; $NetBSD: oosiop.ss,v 1.1 2001/12/05 18:27:13 fredette Exp $
|
||||
; $NetBSD: oosiop.ss,v 1.2 2003/04/06 09:48:42 tsutsui Exp $
|
||||
|
||||
;
|
||||
; Copyright (c) 2001 Matt Fredette
|
||||
; Copyright (c) 1995 Michael L. Hitch
|
||||
; All rights reserved.
|
||||
; Copyright (c) 2001 Shuichiro URATA. All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions
|
||||
|
|
@ -13,11 +11,8 @@
|
|||
; 2. Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; 3. All advertising materials mentioning features or use of this software
|
||||
; must display the following acknowledgement:
|
||||
; This product includes software developed by Michael L. Hitch.
|
||||
; 4. The name of the author may not be used to endorse or promote products
|
||||
; derived from this software without specific prior written permission
|
||||
; 3. The name of the author may not be used to endorse or promote products
|
||||
; derived from this software without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
|
|
@ -33,211 +28,123 @@
|
|||
|
||||
; NCR 53c700 script
|
||||
;
|
||||
|
||||
ARCH 700
|
||||
;
|
||||
EXTERNAL ds_Device
|
||||
EXTERNAL ds_MsgOut
|
||||
EXTERNAL ds_Cmd
|
||||
EXTERNAL ds_Status
|
||||
EXTERNAL ds_Msg
|
||||
EXTERNAL ds_MsgIn
|
||||
EXTERNAL ds_ExtMsg
|
||||
EXTERNAL ds_SyncMsg
|
||||
EXTERNAL ds_Data1
|
||||
|
||||
; interrupt codes
|
||||
ABSOLUTE int_done = 0xbeef0000
|
||||
ABSOLUTE int_msgin = 0xbeef0001
|
||||
ABSOLUTE int_extmsg = 0xbeef0002
|
||||
ABSOLUTE int_resel = 0xbeef0003
|
||||
ABSOLUTE int_res_id = 0xbeef0004
|
||||
ABSOLUTE int_resfail = 0xbeef0005
|
||||
ABSOLUTE int_disc = 0xbeef0006
|
||||
ABSOLUTE int_err = 0xdeadbeef
|
||||
|
||||
; patch entries
|
||||
ENTRY p_resel_msgin_move
|
||||
ENTRY p_select
|
||||
ENTRY p_datain_jump
|
||||
ENTRY p_dataout_jump
|
||||
ENTRY p_msgin_move
|
||||
ENTRY p_msgout_move
|
||||
ENTRY p_cmdout_move
|
||||
ENTRY p_status_move
|
||||
ENTRY p_extmsglen_move
|
||||
ENTRY p_extmsgin_move
|
||||
|
||||
|
||||
ABSOLUTE ok = 0xff00
|
||||
ABSOLUTE int_disc = 0xff01
|
||||
ABSOLUTE int_disc_wodp = 0xff02
|
||||
ABSOLUTE int_reconnect = 0xff03
|
||||
ABSOLUTE int_connect = 0xff04
|
||||
ABSOLUTE int_phase = 0xff05
|
||||
ABSOLUTE int_msgin = 0xff06
|
||||
ABSOLUTE int_extmsg = 0xff07
|
||||
ABSOLUTE int_msgsdp = 0xff08
|
||||
ABSOLUTE int_identify = 0xff09
|
||||
ABSOLUTE int_status = 0xff0a
|
||||
ABSOLUTE int_syncmsg = 0xff0b
|
||||
PROC oosiop_script:
|
||||
|
||||
ENTRY scripts
|
||||
ENTRY switch
|
||||
ENTRY wait_reselect
|
||||
ENTRY dataout
|
||||
ENTRY datain
|
||||
ENTRY clear_ack
|
||||
ENTRY wait_reselect
|
||||
wait_reselect:
|
||||
WAIT RESELECT REL(reselect_fail)
|
||||
INT int_resel
|
||||
reselect_fail:
|
||||
INT int_resfail
|
||||
|
||||
PROC oosiop_script:
|
||||
ENTRY wait_resel_identify
|
||||
wait_resel_identify:
|
||||
INT int_err, WHEN NOT MSG_IN
|
||||
p_resel_msgin_move:
|
||||
MOVE 0, 0, WHEN MSG_IN
|
||||
INT int_res_id
|
||||
|
||||
scripts:
|
||||
ENTRY start_select
|
||||
start_select:
|
||||
p_select:
|
||||
SELECT ATN 0, REL(wait_reselect)
|
||||
|
||||
SELECT ATN ds_Device, reselect
|
||||
;
|
||||
switch:
|
||||
JUMP msgin, WHEN MSG_IN
|
||||
JUMP msgout, IF MSG_OUT
|
||||
JUMP command_phase, IF CMD
|
||||
JUMP dataout, IF DATA_OUT
|
||||
JUMP datain, IF DATA_IN
|
||||
JUMP end, IF STATUS
|
||||
|
||||
INT int_phase ; Unrecognized phase
|
||||
ENTRY phasedispatch
|
||||
phasedispatch:
|
||||
JUMP REL(msgin), WHEN MSG_IN
|
||||
JUMP REL(msgout), WHEN MSG_OUT
|
||||
JUMP REL(status), WHEN STATUS
|
||||
JUMP REL(cmdout), WHEN CMD
|
||||
p_datain_jump:
|
||||
JUMP 0, WHEN DATA_IN
|
||||
p_dataout_jump:
|
||||
JUMP 0, WHEN DATA_OUT
|
||||
INT int_err
|
||||
|
||||
msgin:
|
||||
MOVE 0, ds_MsgIn, WHEN MSG_IN
|
||||
JUMP ext_msg, IF 0x01 ; extended message
|
||||
JUMP disc, IF 0x04 ; disconnect message
|
||||
JUMP msg_sdp, IF 0x02 ; save data pointers
|
||||
JUMP msg_rej, IF 0x07 ; message reject
|
||||
JUMP msg_rdp, IF 0x03 ; restore data pointers
|
||||
INT int_msgin ; unrecognized message
|
||||
|
||||
msg_rej:
|
||||
; Do we need to interrupt host here to let it handle the reject?
|
||||
msg_rdp:
|
||||
clear_ack:
|
||||
CLEAR ACK
|
||||
CLEAR ATN
|
||||
JUMP switch
|
||||
p_msgin_move:
|
||||
MOVE 0, 0, WHEN MSG_IN
|
||||
JUMP REL(complete), IF 0x00
|
||||
JUMP REL(extmsgsetup), IF 0x01
|
||||
JUMP REL(disconnect), IF 0x04
|
||||
INT int_msgin
|
||||
|
||||
ext_msg:
|
||||
ENTRY ack_msgin
|
||||
ack_msgin:
|
||||
CLEAR ACK
|
||||
MOVE 0, ds_ExtMsg, WHEN MSG_IN
|
||||
JUMP sync_msg, IF 0x03
|
||||
int int_extmsg ; extended message not SDTR
|
||||
JUMP REL(phasedispatch)
|
||||
|
||||
sync_msg:
|
||||
CLEAR ACK
|
||||
MOVE 0, ds_SyncMsg, WHEN MSG_IN
|
||||
int int_syncmsg ; Let host handle the message
|
||||
; If we continue from the interrupt, the host has set up a response
|
||||
; message to be sent. Set ATN, clear ACK, and continue.
|
||||
ENTRY sendmsg
|
||||
sendmsg:
|
||||
SET ATN
|
||||
CLEAR ACK
|
||||
JUMP switch
|
||||
|
||||
disc:
|
||||
CLEAR ACK
|
||||
WAIT DISCONNECT
|
||||
|
||||
int int_disc_wodp ; signal disconnect w/o save DP
|
||||
|
||||
msg_sdp:
|
||||
CLEAR ACK ; acknowledge message
|
||||
JUMP switch, WHEN NOT MSG_IN
|
||||
MOVE 0, ds_ExtMsg, WHEN MSG_IN
|
||||
INT int_msgsdp, IF NOT 0x04 ; interrupt if not disconnect
|
||||
CLEAR ACK
|
||||
WAIT DISCONNECT
|
||||
|
||||
INT int_disc ; signal disconnect
|
||||
|
||||
reselect:
|
||||
wait_reselect:
|
||||
WAIT RESELECT select_adr
|
||||
; NB: these NOPs are CRITICAL to preserve the 1:1
|
||||
; correspondence between instructions in this script
|
||||
; and instructions in the osiop (53c710) script:
|
||||
NOP
|
||||
NOP ; reselect ID already in SFBR
|
||||
|
||||
INT int_identify, WHEN NOT MSG_IN
|
||||
MOVE 0, ds_Msg, WHEN MSG_IN
|
||||
INT int_reconnect ; let host know about reconnect
|
||||
CLEAR ACK ; acknowlege the message
|
||||
JUMP switch
|
||||
|
||||
select_adr:
|
||||
MOVE SCNTL1 & 0x10 to SFBR ; get connected status
|
||||
INT int_connect, IF 0x00 ; tell host if not connected
|
||||
NOP ; Sig_P doesn't exist on the 53c700
|
||||
JUMP wait_reselect ; and try reselect again
|
||||
|
||||
msgout:
|
||||
MOVE 0, ds_MsgOut, WHEN MSG_OUT
|
||||
JUMP switch
|
||||
|
||||
command_phase:
|
||||
p_msgout_move:
|
||||
MOVE 0, 0, WHEN MSG_OUT
|
||||
CLEAR ATN
|
||||
MOVE 0, ds_Cmd, WHEN CMD
|
||||
JUMP switch
|
||||
JUMP REL(phasedispatch)
|
||||
|
||||
dataout:
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch, WHEN NOT DATA_OUT
|
||||
MOVE 0, ds_Data1, WHEN DATA_OUT
|
||||
CALL switch
|
||||
cmdout:
|
||||
CLEAR ATN
|
||||
p_cmdout_move:
|
||||
MOVE 0, 0, WHEN CMD
|
||||
JUMP REL(phasedispatch)
|
||||
|
||||
datain:
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch, WHEN NOT DATA_IN
|
||||
MOVE 0, ds_Data1, WHEN DATA_IN
|
||||
CALL switch
|
||||
status:
|
||||
p_status_move:
|
||||
MOVE 0, 0, WHEN STATUS
|
||||
JUMP REL(phasedispatch)
|
||||
|
||||
end:
|
||||
MOVE 0, ds_Status, WHEN STATUS
|
||||
int int_status, WHEN NOT MSG_IN ; status not followed by msg
|
||||
MOVE 0, ds_Msg, WHEN MSG_IN
|
||||
disconnect:
|
||||
CLEAR ACK
|
||||
WAIT DISCONNECT
|
||||
INT ok ; signal completion
|
||||
JUMP wait_reselect
|
||||
INT int_disc
|
||||
|
||||
complete:
|
||||
CLEAR ACK
|
||||
WAIT DISCONNECT
|
||||
INT int_done
|
||||
|
||||
; receive extended message length
|
||||
extmsgsetup:
|
||||
CLEAR ACK
|
||||
INT int_err, IF NOT MSG_IN
|
||||
p_extmsglen_move:
|
||||
MOVE 0, 0, WHEN MSG_IN
|
||||
INT int_extmsg
|
||||
|
||||
; receive extended message
|
||||
ENTRY rcv_extmsg
|
||||
rcv_extmsg:
|
||||
CLEAR ACK
|
||||
INT int_err, IF NOT MSG_IN
|
||||
p_extmsgin_move:
|
||||
MOVE 0, 0, WHEN MSG_IN
|
||||
INT int_msgin
|
||||
|
|
|
|||
Loading…
Reference in New Issue