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Add a routine to set the mpu multiplier. (not used yet)

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This commit is contained in:
matt 2013-06-28 02:31:16 +00:00
parent 6fb884f892
commit 7b3bf49e93
2 changed files with 49 additions and 3 deletions
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34
sys/arch/arm/omap/am335x_prcm.c
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@ -1,4 +1,4 @@
/* $NetBSD: am335x_prcm.c,v 1.1 2012/12/11 18:53:26 riastradh Exp $ */
/* $NetBSD: am335x_prcm.c,v 1.2 2013/06/28 02:31:16 matt Exp $ */
/*
* TI OMAP Power, Reset, and Clock Management on the AM335x
@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: am335x_prcm.c,v 1.1 2012/12/11 18:53:26 riastradh Exp $");
__KERNEL_RCSID(0, "$NetBSD: am335x_prcm.c,v 1.2 2013/06/28 02:31:16 matt Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -93,3 +93,33 @@ prcm_module_disable(const struct omap_module *om)
prcm_write_4(cm_module, clkctrl_reg, clkctrl);
am335x_prcm_check_clkctrl(cm_module, clkctrl_reg, clkctrl);
}
void
prcm_mpu_pll_config(u_int mpupll_m)
{
uint32_t clkmode = prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKMODE_DPLL_MPU);
uint32_t clksel = prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKSEL_DPLL_MPU);
//uint32_t div_m2 = prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_DIV_M2_DPLL_MPU);
/* Request the DPLL to be put into bypass mode */
prcm_write_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKMODE_DPLL_MPU, AM335X_PRCM_CM_CLKMODE_DPLL_MN_BYP_MODE);
/* Wait for it to be put into bypass */
while (prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_IDLEST_DPLL_MPU) != AM335X_PRCM_CM_IDLEST_DPLL_ST_DPLL_CLK_MN_BYPASS) {
/* nothing */
}
/* Replace multipler */
clksel &= ~AM335X_PRCM_CM_CLKSEL_DPLL_MULT;
clksel |= __SHIFTIN(mpupll_m, AM335X_PRCM_CM_CLKSEL_DPLL_MULT);
prcm_write_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKSEL_DPLL_MPU, clksel);
/* Exit bypass mode */
clkmode |= AM335X_PRCM_CM_CLKMODE_DPLL_LOCK_MODE;
prcm_write_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKMODE_DPLL_MPU, clkmode);
/* Wait for the DPLL to lock */
while (prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_IDLEST_DPLL_MPU) != AM335X_PRCM_CM_IDLEST_DPLL_ST_DPLL_CLK_LOCKED) {
/* nothing */
}
}

18
sys/arch/arm/omap/am335x_prcm.h
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@ -1,4 +1,4 @@
/* $NetBSD: am335x_prcm.h,v 1.2 2012/12/13 02:12:15 jakllsch Exp $ */
/* $NetBSD: am335x_prcm.h,v 1.3 2013/06/28 02:31:16 matt Exp $ */
/*
* TI OMAP Power, Reset, and Clock Management on the AM335x
@ -61,8 +61,24 @@ struct omap_module {
#define AM335X_PRCM_PRM_GFX 0x1100
#define AM335X_PRCM_PRM_CEFUSE 0x1200
/* In CM_WKUP */
#define AM335X_PRCM_CM_IDLEST_DPLL_MPU 0x20
#define AM335X_PRCM_CM_IDLEST_DPLL_ST_DPLL_CLK_MN_BYPASS __BIT(8)
#define AM335X_PRCM_CM_IDLEST_DPLL_ST_DPLL_CLK_LOCKED __BIT(0)
#define AM335X_PRCM_CM_CLKSEL_DPLL_MPU 0x2c
#define AM335X_PRCM_CM_CLKSEL_DPLL_BYPASS __BITS(23)
#define AM335X_PRCM_CM_CLKSEL_DPLL_MULT __BITS(18,8)
#define AM335X_PRCM_CM_CLKSEL_DPLL_DIV __BITS(6,0)
#define AM335X_PRCM_CM_CLKMODE_DPLL_MPU 0x88
#define AM335X_PRCM_CM_CLKMODE_DPLL_MN_BYP_MODE 4
#define AM335X_PRCM_CM_CLKMODE_DPLL_LOCK_MODE 7
#define AM335X_PRCM_CM_DIV_M2_DPLL_MPU 0xa8
#define PRM_RSTCTRL 0x00 /* offset from AM335X_PRCM_PRM_DEVICE */
#define RST_GLOBAL_WARM_SW __BIT(0)
#define RST_GLOBAL_COLD_SW __BIT(1)
void prcm_mpu_pll_config(u_int);
#endif /* _ARM_OMAP_AM335X_PRCM_H_ */