Various, including:
* Add more delays while writing registers.
* Replace sc_dma{in,out}_inprogress with sc_dmadir.
* Eliminate the need for sc_locked.
* Add more DPRINTF()s.
This commit is contained in:
mycroft
parent
faf2b8bb49
commit
7af4edd731
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@ -1,4 +1,4 @@
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/* $NetBSD: sbdsp.c,v 1.14 1995/11/10 05:01:06 mycroft Exp $ */
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/* $NetBSD: sbdsp.c,v 1.15 1996/02/16 08:07:40 mycroft Exp $ */
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/*
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* Copyright (c) 1991-1993 Regents of the University of California.
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@ -87,8 +87,8 @@ sb_printsc(struct sbdsp_softc *sc)
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{
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int i;
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printf("open %d dmachan %d iobase %x locked %d\n", sc->sc_open, sc->sc_drq,
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sc->sc_iobase, sc->sc_locked);
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printf("open %d dmachan %d iobase %x\n", sc->sc_open, sc->sc_drq,
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sc->sc_iobase);
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printf("hispeed %d irate %d orate %d encoding %x\n",
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sc->sc_adacmode, sc->sc_irate, sc->sc_orate, sc->encoding);
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printf("outport %d inport %d spkron %d nintr %d\n",
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@ -134,8 +134,6 @@ sbdsp_attach(sc)
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{
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register int iobase = sc->sc_iobase;
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sc->sc_locked = 0;
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/* Set defaults */
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if (ISSBPROCLASS(sc))
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sc->sc_irate = sc->sc_orate = 45454;
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@ -223,9 +221,9 @@ sbdsp_set_in_sr_real(addr, sr)
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if (rval = sbdsp_set_sr(sc, &sr, SB_INPUT_RATE))
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return rval;
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sc->sc_irate = sr;
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sc->sc_dmain_inprogress = 0; /* do it again on next DMA out */
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sc->sc_dmaout_inprogress = 0;
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return(0);
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if (sc->sc_dmadir == SBP_DMA_IN)
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sc->sc_dmadir = SBP_DMA_NONE; /* do it again on next DMA in */
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return 0;
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}
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u_long
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@ -259,8 +257,9 @@ sbdsp_set_out_sr_real(addr, sr)
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if (rval = sbdsp_set_sr(sc, &sr, SB_OUTPUT_RATE))
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return rval;
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sc->sc_orate = sr;
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sc->sc_dmain_inprogress = 0; /* do it again on next DMA out */
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return(0);
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if (sc->sc_dmadir == SBP_DMA_OUT)
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sc->sc_dmadir = SBP_DMA_NONE; /* do it again on next DMA out */
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return 0;
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}
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u_long
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@ -511,7 +510,7 @@ sbdsp_round_blocksize(addr, blk)
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{
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register struct sbdsp_softc *sc = addr;
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sc->sc_last_hsr_size = sc->sc_last_hsw_size = 0;
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sc->sc_last_hs_size = 0;
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/* Higher speeds need bigger blocks to avoid popping and silence gaps. */
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if ((sc->sc_orate > 8000 || sc->sc_irate > 8000) &&
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@ -539,8 +538,7 @@ sbdsp_commit_settings(addr)
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sbdsp_set_out_sr_real(addr, sc->sc_orate);
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sbdsp_set_in_sr_real(addr, sc->sc_irate);
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sc->sc_last_hsw_size = sc->sc_last_hsr_size = 0;
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return(0);
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return 0;
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}
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@ -557,16 +555,11 @@ sbdsp_open(sc, dev, flags)
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sc->sc_open = 1;
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sc->sc_mintr = 0;
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sc->sc_intr = 0;
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sc->sc_arg = 0;
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sc->sc_locked = 0;
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if (ISSBPROCLASS(sc) &&
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sbdsp_wdsp(sc->sc_iobase, SB_DSP_RECORD_MONO) < 0) {
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DPRINTF(("sbdsp_open: can't set mono mode\n"));
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/* we'll readjust when it's time for DMA. */
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}
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sc->sc_dmain_inprogress = 0;
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sc->sc_dmaout_inprogress = 0;
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/*
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* Leave most things as they were; users must change things if
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@ -590,10 +583,8 @@ sbdsp_close(addr)
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sc->sc_open = 0;
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sbdsp_spkroff(sc);
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sc->spkr_state = SPKR_OFF;
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sc->sc_intr = 0;
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sc->sc_mintr = 0;
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/* XXX this will turn off any dma */
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sbdsp_reset(sc);
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sbdsp_haltdma(sc);
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DPRINTF(("sbdsp_close: closed\n"));
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}
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@ -612,20 +603,25 @@ sbdsp_reset(sc)
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{
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register int iobase = sc->sc_iobase;
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/*
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* erase any memory of last transfer size.
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*/
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sc->sc_last_hsr_size = sc->sc_last_hsw_size = 0;
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sc->sc_intr = 0;
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if (sc->sc_dmadir != SBP_DMA_NONE) {
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isa_dmaabort(sc->sc_drq);
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sc->sc_dmadir = SBP_DMA_NONE;
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}
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sc->sc_last_hs_size = 0;
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/*
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* See SBK, section 11.3.
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* We pulse a reset signal into the card.
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* Gee, what a brilliant hardware design.
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*/
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outb(iobase + SBP_DSP_RESET, 1);
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delay(3);
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delay(10);
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outb(iobase + SBP_DSP_RESET, 0);
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delay(30);
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if (sbdsp_rdsp(iobase) != SB_MAGIC)
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return -1;
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return 0;
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}
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@ -640,10 +636,13 @@ sbdsp_wdsp(int iobase, int v)
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register int i;
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for (i = SBDSP_NPOLL; --i >= 0; ) {
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if ((inb(iobase + SBP_DSP_WSTAT) & SB_DSP_BUSY) != 0) {
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delay(10); continue;
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}
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register u_char x;
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x = inb(iobase + SBP_DSP_WSTAT);
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delay(10);
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if ((x & SB_DSP_BUSY) != 0)
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continue;
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outb(iobase + SBP_DSP_WRITE, v);
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delay(10);
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return 0;
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}
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++sberr.wdsp;
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@ -659,9 +658,14 @@ sbdsp_rdsp(int iobase)
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register int i;
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for (i = SBDSP_NPOLL; --i >= 0; ) {
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if ((inb(iobase + SBP_DSP_RSTAT) & SB_DSP_READY) == 0)
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register u_char x;
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x = inb(iobase + SBP_DSP_RSTAT);
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delay(10);
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if ((x & SB_DSP_READY) == 0)
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continue;
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return inb(iobase + SBP_DSP_READ);
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x = inb(iobase + SBP_DSP_READ);
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delay(10);
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return x;
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}
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++sberr.rdsp;
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return -1;
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@ -747,18 +751,8 @@ sbdsp_haltdma(addr)
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DPRINTF(("sbdsp_haltdma: sc=0x%x\n", sc));
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if (sc->sc_locked)
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sbdsp_reset(sc);
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else
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(void)sbdsp_wdsp(sc->sc_iobase, SB_DSP_HALT);
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isa_dmaabort(sc->sc_drq);
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sc->dmaaddr = 0;
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sc->dmacnt = 0;
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sc->sc_locked = 0;
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sc->dmaflags = 0;
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sc->sc_dmain_inprogress = sc->sc_dmaout_inprogress = 0;
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return(0);
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sbdsp_reset(sc);
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return 0;
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}
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int
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@ -950,30 +944,25 @@ sbdsp_dma_input(addr, p, cc, intr, arg)
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DPRINTF(("sbdsp_dma_input: stereo input, odd bytecnt\n"));
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return EIO;
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}
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iobase = sc->sc_iobase;
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if (ISSBPROCLASS(sc) && !sc->sc_dmain_inprogress) {
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if (ISSBPROCLASS(sc) && sc->sc_dmadir != SBP_DMA_IN) {
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if (sc->sc_chans == 2) {
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if (sbdsp_wdsp(iobase, SB_DSP_RECORD_STEREO) < 0)
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goto badmode;
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sbdsp_mix_write(sc, SBP_STEREO,
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sbdsp_mix_read(sc, SBP_STEREO) & ~SBP_PLAYMODE_MASK);
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sbdsp_mix_write(sc, SBP_INFILTER,
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sbdsp_mix_read(sc, SBP_INFILTER) | SBP_FILTER_OFF);
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}
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else {
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if (sbdsp_wdsp(iobase, SB_DSP_RECORD_MONO) < 0)
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goto badmode;
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sbdsp_mix_write(sc, SBP_STEREO,
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sbdsp_mix_read(sc, SBP_STEREO) & ~SBP_PLAYMODE_MASK);
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sbdsp_mix_write(sc, SBP_INFILTER,
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sc->sc_irate <= 8000 ?
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sbdsp_mix_read(sc, SBP_INFILTER) & ~SBP_FILTER_MASK :
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sbdsp_mix_read(sc, SBP_INFILTER) | SBP_FILTER_OFF);
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}
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sc->sc_dmain_inprogress = 1;
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sc->sc_last_hsr_size = 0; /* restarting */
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sc->sc_dmadir = SBP_DMA_IN;
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}
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sc->sc_dmaout_inprogress = 0;
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isa_dmastart(B_READ, p, cc, sc->sc_drq);
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sc->sc_intr = intr;
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@ -981,33 +970,36 @@ sbdsp_dma_input(addr, p, cc, intr, arg)
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sc->dmaflags = B_READ;
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sc->dmaaddr = p;
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sc->dmacnt = --cc; /* DMA controller is strange...? */
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if (sc->sc_adacmode == SB_ADAC_LS) {
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if (sbdsp_wdsp(iobase, SB_DSP_RDMA) < 0 ||
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sbdsp_wdsp(iobase, cc) < 0 ||
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sbdsp_wdsp(iobase, cc >> 8) < 0) {
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DPRINTF(("sbdsp_dma_input: LS DMA start failed\n"));
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goto giveup;
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}
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}
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else {
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if (cc != sc->sc_last_hsr_size) {
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if (cc != sc->sc_last_hs_size) {
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if (sbdsp_wdsp(iobase, SB_DSP_BLOCKSIZE) < 0 ||
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sbdsp_wdsp(iobase, cc) < 0 ||
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sbdsp_wdsp(iobase, cc >> 8) < 0)
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sbdsp_wdsp(iobase, cc >> 8) < 0) {
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DPRINTF(("sbdsp_dma_input: HS DMA start failed\n"));
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goto giveup;
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}
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sc->sc_last_hs_size = cc;
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}
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if (sbdsp_wdsp(iobase, SB_DSP_HS_INPUT) < 0)
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if (sbdsp_wdsp(iobase, SB_DSP_HS_INPUT) < 0) {
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DPRINTF(("sbdsp_dma_input: HS DMA restart failed\n"));
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goto giveup;
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sc->sc_last_hsr_size = cc;
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sc->sc_locked = 1;
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}
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}
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return 0;
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giveup:
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isa_dmaabort(sc->sc_drq);
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sbdsp_reset(sc);
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sc->sc_intr = 0;
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sc->sc_arg = 0;
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return EIO;
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badmode:
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DPRINTF(("sbdsp_dma_input: can't set %s mode\n",
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sc->sc_chans == 2 ? "stereo" : "mono"));
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@ -1029,22 +1021,22 @@ sbdsp_dma_output(addr, p, cc, intr, arg)
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if (sbdspdebug > 1)
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Dprintf("sbdsp_dma_output: cc=%d 0x%x (0x%x)\n", cc, intr, arg);
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#endif
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if (sc->sc_chans == 2 && cc & 1) {
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if (sc->sc_chans == 2 && (cc & 1)) {
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DPRINTF(("stereo playback odd bytes (%d)\n", cc));
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return EIO;
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}
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if (ISSBPROCLASS(sc) && !sc->sc_dmaout_inprogress) {
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iobase = sc->sc_iobase;
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if (ISSBPROCLASS(sc) && sc->sc_dmadir != SBP_DMA_OUT) {
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/* make sure we re-set stereo mixer bit when we start
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output. */
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sbdsp_mix_write(sc, SBP_STEREO,
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(sbdsp_mix_read(sc, SBP_STEREO) & ~SBP_PLAYMODE_MASK) |
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(sc->sc_chans == 2 ?
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SBP_PLAYMODE_STEREO : SBP_PLAYMODE_MONO));
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sc->sc_dmaout_inprogress = 1;
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sc->sc_last_hsw_size = 0; /* restarting */
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sc->sc_dmadir = SBP_DMA_OUT;
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}
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sc->sc_dmain_inprogress = 0;
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isa_dmastart(B_WRITE, p, cc, sc->sc_drq);
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sc->sc_intr = intr;
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sc->sc_arg = arg;
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@ -1052,7 +1044,6 @@ sbdsp_dma_output(addr, p, cc, intr, arg)
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sc->dmaaddr = p;
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sc->dmacnt = --cc; /* a vagary of how DMA works, apparently. */
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iobase = sc->sc_iobase;
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if (sc->sc_adacmode == SB_ADAC_LS) {
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if (sbdsp_wdsp(iobase, SB_DSP_WDMA) < 0 ||
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sbdsp_wdsp(iobase, cc) < 0 ||
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@ -1062,39 +1053,24 @@ sbdsp_dma_output(addr, p, cc, intr, arg)
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}
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}
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else {
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if (cc != sc->sc_last_hsw_size) {
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if (sbdsp_wdsp(iobase, SB_DSP_BLOCKSIZE) < 0) {
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/* sometimes fails initial startup?? */
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delay(100);
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if (sbdsp_wdsp(iobase, SB_DSP_BLOCKSIZE) < 0) {
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DPRINTF(("sbdsp_dma_output: BLOCKSIZE failed\n"));
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goto giveup;
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}
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}
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if (sbdsp_wdsp(iobase, cc) < 0 ||
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if (cc != sc->sc_last_hs_size) {
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if (sbdsp_wdsp(iobase, SB_DSP_BLOCKSIZE) < 0 ||
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sbdsp_wdsp(iobase, cc) < 0 ||
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sbdsp_wdsp(iobase, cc >> 8) < 0) {
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DPRINTF(("sbdsp_dma_output: HS DMA start failed\n"));
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goto giveup;
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}
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sc->sc_last_hsw_size = cc;
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sc->sc_last_hs_size = cc;
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}
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if (sbdsp_wdsp(iobase, SB_DSP_HS_OUTPUT) < 0) {
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delay(100);
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if (sbdsp_wdsp(iobase, SB_DSP_HS_OUTPUT) < 0) {
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DPRINTF(("sbdsp_dma_output: HS DMA restart failed\n"));
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goto giveup;
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}
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DPRINTF(("sbdsp_dma_output: HS DMA restart failed\n"));
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goto giveup;
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}
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sc->sc_locked = 1;
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}
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|
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return 0;
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giveup:
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isa_dmaabort(sc->sc_drq);
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giveup:
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sbdsp_reset(sc);
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sc->sc_intr = 0;
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sc->sc_arg = 0;
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return EIO;
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}
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|
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@ -1110,36 +1086,40 @@ sbdsp_intr(arg)
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void *arg;
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{
|
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register struct sbdsp_softc *sc = arg;
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u_char x;
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|
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#ifdef AUDIO_DEBUG
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if (sbdspdebug > 1)
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Dprintf("sbdsp_intr: intr=0x%x\n", sc->sc_intr);
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#endif
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sc->sc_interrupts++;
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sc->sc_locked = 0;
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/* clear interrupt */
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inb(sc->sc_iobase + SBP_DSP_RSTAT);
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x = inb(sc->sc_iobase + SBP_DSP_RSTAT);
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delay(10);
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#if 0
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if ((x & SB_DSP_READY) == 0) {
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printf("sbdsp_intr: still busy\n");
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return 0;
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}
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#endif
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#if 0
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if (sc->sc_mintr != 0) {
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int c = sbdsp_rdsp(sc->sc_iobase);
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(*sc->sc_mintr)(sc->sc_arg, c);
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x = sbdsp_rdsp(sc->sc_iobase);
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(*sc->sc_mintr)(sc->sc_arg, x);
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} else
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#endif
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if (sc->sc_intr != 0) {
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/*
|
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* The SBPro used to develop and test this driver often
|
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* generated dma underruns--it interrupted to signal
|
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* completion of the DMA input recording block, but the
|
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* ISA DMA controller didn't think the channel was
|
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* finished. Maybe this is just a bus speed issue, I dunno,
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* but it seems strange and leads to channel-flipping with stereo
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* recording. Sigh.
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*/
|
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/*
|
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* The SBPro used to develop and test this driver often
|
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* generated dma underruns--it interrupted to signal
|
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* completion of the DMA input recording block, but the
|
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* ISA DMA controller didn't think the channel was
|
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* finished. Maybe this is just a bus speed issue, I dunno,
|
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* but it seems strange and leads to channel-flipping with
|
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* stereo recording. Sigh.
|
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*/
|
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isa_dmadone(sc->dmaflags, sc->dmaaddr, sc->dmacnt,
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sc->sc_drq);
|
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sc->dmaflags = 0;
|
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sc->dmaaddr = 0;
|
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sc->dmacnt = 0;
|
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(*sc->sc_intr)(sc->sc_arg);
|
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}
|
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else
|
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|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
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/* $NetBSD: sbdspvar.h,v 1.7 1995/11/10 05:01:08 mycroft Exp $ */
|
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/* $NetBSD: sbdspvar.h,v 1.8 1996/02/16 08:07:46 mycroft Exp $ */
|
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|
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/*
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* Copyright (c) 1991-1993 Regents of the University of California.
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@ -80,7 +80,6 @@ struct sbdsp_softc {
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int sc_drq; /* DMA */
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||||
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||||
u_short sc_open; /* reference count of open calls */
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u_short sc_locked; /* true when doing HS DMA */
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||||
u_short sc_adacmode; /* low/high speed mode indicator */
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||||
u_long sc_irate; /* Sample rate for input */
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||||
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|
@ -107,11 +106,12 @@ struct sbdsp_softc {
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int dmaflags;
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||||
caddr_t dmaaddr;
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||||
vm_size_t dmacnt;
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||||
int sc_last_hsw_size; /* last HS dma size */
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||||
int sc_last_hsr_size; /* last HS dma size */
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||||
int sc_last_hs_size; /* last HS dma size */
|
||||
int sc_chans; /* # of channels */
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||||
char sc_dmain_inprogress; /* DMA input in progress? */
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||||
char sc_dmaout_inprogress; /* DMA output in progress? */
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||||
int sc_dmadir; /* DMA direction */
|
||||
#define SBP_DMA_NONE 0
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||||
#define SBP_DMA_IN 1
|
||||
#define SBP_DMA_OUT 2
|
||||
|
||||
u_int sc_model; /* DSP model */
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||||
#define SBVER_MAJOR(v) ((v)>>8)
|
||||
|
|
|
|||
Loading…
Reference in New Issue