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SuperSPARCs without cache controller need some extra cache flushs 

With this a MULTIPROCESSOR kernel works again with a pair of SM50
This commit is contained in:
macallan 2007-07-31 05:21:47 +00:00
parent 173e0805ea
commit 7add3da5f4
2 changed files with 10 additions and 7 deletions
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10
sys/arch/sparc/sparc/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.203 2007/05/28 21:24:17 mrg Exp $ */
/* $NetBSD: cpu.c,v 1.204 2007/07/31 05:21:47 macallan Exp $ */
/*
* Copyright (c) 1996
@ -52,7 +52,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.203 2007/05/28 21:24:17 mrg Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.204 2007/07/31 05:21:47 macallan Exp $");
#include "opt_multiprocessor.h"
#include "opt_lockdebug.h"
@ -1723,9 +1723,11 @@ static int mxcc = -1;
else
sc->flags |= CPUFLG_CACHEPAGETABLES;
} else {
sc->cache_flush = viking_cache_flush;
#ifdef MULTIPROCESSOR
if (sparc_ncpus > 1)
sc->cache_flush = srmmu_cache_flush;
#endif
}
/* Check all modules have the same MXCC configuration */
if (mxcc != -1 && sc->mxcc != mxcc)
panic("MXCC module mismatch");

7
sys/arch/sparc/sparc/iommu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: iommu.c,v 1.86 2007/03/17 13:51:46 msaitoh Exp $ */
/* $NetBSD: iommu.c,v 1.87 2007/07/31 05:21:47 macallan Exp $ */
/*
* Copyright (c) 1996
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: iommu.c,v 1.86 2007/03/17 13:51:46 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: iommu.c,v 1.87 2007/07/31 05:21:47 macallan Exp $");
#include "opt_sparc_arch.h"
@ -579,7 +579,8 @@ iommu_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map,
&dva, &sgsize)) != 0)
return (error);
if (sc->sc_cachecoherent == 0)
if ((sc->sc_cachecoherent == 0) ||
(curcpu()->cpu_type == CPUTYP_SS1_MBUS_NOMXCC))
cache_flush(buf, buflen); /* XXX - move to bus_dma_sync? */
/*