Don't use EIMC_OTHER bit because it's read only other than 82598.
Documents say: 82598: All of bit 31(OTHER bit) of EIxx are reserved. In reality, at least EIMS_OTHER and EIMC_OTHER exist and the OTHER interrupt doesn't work without EIMS_OTHER. Other than 82598: EIMS_OTHER is read only and EIMC_OTHER doesn't exist. If one of bit 29..16 is set, EIMS_OTHER is set to 1 (Note that bit 30(TCP timer isn't included)). Even if write bit 31 of EIMC to 1, it's ignored (EIMS_OTHER doesn't set). We introduced new spin mutex in ixgbe.c rev. 1.260, so it's OK to remove EIMC_OTHER stuff. We already set EIMS_OTHER in if_init(), so keep it for 82598. No functional change other than 82598. Another solution is to control bit 30..16 directly to mask/unmask interrupt instead of the mutex. TODO: Some MSI-X interrupt(LSC, module insertion/removal etc.)'s mask/unmask code between ixgbe_msix_admin() and ixgbe_handle_admin() may be wrong. It'll be fixed later.
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@ -1,4 +1,4 @@
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/* $NetBSD: ixgbe.c,v 1.261 2020/11/30 07:53:42 msaitoh Exp $ */
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/* $NetBSD: ixgbe.c,v 1.262 2020/12/11 05:01:19 msaitoh Exp $ */
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/******************************************************************************
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@ -3095,9 +3095,6 @@ ixgbe_msix_admin(void *arg)
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++adapter->admin_irqev.ev_count;
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/* Pause other interrupts */
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IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER);
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/* First get the cause */
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/*
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* The specifications of 82598, 82599, X540 and X550 say EICS register
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@ -3219,9 +3216,6 @@ ixgbe_msix_admin(void *arg)
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adapter->task_requests |= task_requests;
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ixgbe_schedule_admin_tasklet(adapter);
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mutex_exit(&adapter->admin_mtx);
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} else {
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/* Re-enable other interrupts */
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IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
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}
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return 1;
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@ -4809,7 +4803,6 @@ ixgbe_handle_admin(struct work *wk, void *context)
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{
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struct adapter *adapter = context;
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struct ifnet *ifp = adapter->ifp;
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struct ixgbe_hw *hw = &adapter->hw;
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u32 task_requests;
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mutex_enter(&adapter->admin_mtx);
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@ -4848,11 +4841,12 @@ ixgbe_handle_admin(struct work *wk, void *context)
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}
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#endif
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if ((task_requests & IXGBE_REQUEST_TASK_NEED_ACKINTR) != 0) {
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if ((adapter->feat_en & IXGBE_FEATURE_MSIX) != 0) {
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/* Re-enable other interrupts */
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IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
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} else
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ixgbe_enable_intr(adapter);
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/*
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* XXX FIXME.
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* ixgbe_enable_intr() enables all interrupts. It might enable
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* an interrupt which should not be enabled.
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*/
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ixgbe_enable_intr(adapter);
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}
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IXGBE_CORE_UNLOCK(adapter);
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@ -1,4 +1,4 @@
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/* $NetBSD: ixgbe_type.h,v 1.45 2020/08/31 11:19:54 msaitoh Exp $ */
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/* $NetBSD: ixgbe_type.h,v 1.46 2020/12/11 05:01:19 msaitoh Exp $ */
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/******************************************************************************
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SPDX-License-Identifier: BSD-3-Clause
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@ -1998,6 +1998,13 @@ enum {
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#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
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#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
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#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
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/*
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* EIMS_OTHER is R/W on 82598 though the document says it's reserved.
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* It MUST be required to set this bit to get OTHER interrupt.
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*
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* On other chips, it's read only. It's set if any bits of 29..16 is not zero.
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* Bit 30 (TCP_TIMER) doesn't affect to EIMS_OTHER.
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*/
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#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
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/* Extended Interrupt Mask Clear */
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@ -2019,6 +2026,7 @@ enum {
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#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
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#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
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#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
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/* EIMC_OTHER works only on 82598. See EIMS_OTHER's comment */
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#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
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#define IXGBE_EIMS_ENABLE_MASK ( \
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