Add support for the Intel G45 AGP. From Arnaud Lacombe
This commit is contained in:
christos
parent
ff6575a088
commit
78b9002948
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@ -1,4 +1,4 @@
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/* $NetBSD: pchb.c,v 1.15 2008/11/08 17:26:28 christos Exp $ */
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/* $NetBSD: pchb.c,v 1.16 2008/11/29 23:48:12 christos Exp $ */
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/*-
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* Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.15 2008/11/08 17:26:28 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.16 2008/11/29 23:48:12 christos Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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@ -383,6 +383,7 @@ pchbattach(device_t parent, device_t self, void *aux)
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case PCI_PRODUCT_INTEL_82G33_HB:
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case PCI_PRODUCT_INTEL_82Q33_HB:
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case PCI_PRODUCT_INTEL_82G35_HB:
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case PCI_PRODUCT_INTEL_82GM45_HB:
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/*
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* The host bridge is either in GFX mode (internal
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* graphics) or in AGP mode. In GFX mode, we pretend
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@ -1,4 +1,4 @@
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/* $NetBSD: agp.c,v 1.63 2008/11/08 17:26:28 christos Exp $ */
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/* $NetBSD: agp.c,v 1.64 2008/11/29 23:48:12 christos Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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@ -65,7 +65,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.63 2008/11/08 17:26:28 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.64 2008/11/29 23:48:12 christos Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -184,6 +184,8 @@ const struct agp_product {
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NULL, agp_i810_attach },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82946GZ_HB,
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NULL, agp_i810_attach },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82GM45_HB,
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NULL, agp_i810_attach },
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#endif
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#if NAGP_INTEL > 0
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@ -1,4 +1,4 @@
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/* $NetBSD: agp_i810.c,v 1.57 2008/11/08 17:26:28 christos Exp $ */
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/* $NetBSD: agp_i810.c,v 1.58 2008/11/29 23:48:12 christos Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.57 2008/11/08 17:26:28 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.58 2008/11/29 23:48:12 christos Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -57,22 +57,6 @@ __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.57 2008/11/08 17:26:28 christos Exp $
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#define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off)
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#define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off)
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#define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v)
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#define WRITEGTT(off, v) \
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do { \
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if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \
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bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \
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(u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \
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(v)); \
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} else if (isc->chiptype == CHIP_I965) { \
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WRITE4(AGP_I965_GTT + \
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(u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \
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(v)); \
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} else { \
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WRITE4(AGP_I810_GTT + \
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(u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \
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(v)); \
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} \
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} while (0)
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#define CHIP_I810 0 /* i810/i815 */
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#define CHIP_I830 1 /* 830M/845G */
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@ -80,6 +64,7 @@ __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.57 2008/11/08 17:26:28 christos Exp $
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#define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */
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#define CHIP_I965 4 /* 965Q/965PM */
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#define CHIP_G33 5 /* G33/Q33/Q35 */
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#define CHIP_G4X 6 /* G45/Q45 */
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struct agp_i810_softc {
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u_int32_t initial_aperture; /* aperture size at startup */
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@ -117,6 +102,8 @@ static bool agp_i810_resume(device_t PMF_FN_PROTO);
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static int agp_i810_init(struct agp_softc *);
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static int agp_i810_init(struct agp_softc *);
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static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t,
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u_int32_t);
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static struct agp_methods agp_i810_methods = {
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agp_i810_get_aperture,
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@ -131,6 +118,33 @@ static struct agp_methods agp_i810_methods = {
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agp_i810_unbind_memory,
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};
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static void
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agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v)
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{
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u_int32_t base_off;
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base_off = 0;
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switch (isc->chiptype) {
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case CHIP_I810:
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case CHIP_I830:
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case CHIP_I855:
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base_off = AGP_I810_GTT;
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break;
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case CHIP_I965:
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base_off = AGP_I965_GTT;
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break;
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case CHIP_G4X:
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base_off = AGP_G4X_GTT;
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break;
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case CHIP_I915:
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case CHIP_G33:
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break;
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}
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WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v);
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}
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/* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */
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static int
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agp_i810_vgamatch(struct pci_attach_args *pa)
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@ -170,6 +184,8 @@ agp_i810_vgamatch(struct pci_attach_args *pa)
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case PCI_PRODUCT_INTEL_82G35_IGD:
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case PCI_PRODUCT_INTEL_82G35_IGD_1:
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case PCI_PRODUCT_INTEL_82946GZ_IGD:
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case PCI_PRODUCT_INTEL_82GM45_IGD:
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case PCI_PRODUCT_INTEL_82GM45_IGD_1:
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return (1);
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}
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@ -272,6 +288,9 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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case PCI_PRODUCT_INTEL_82Q33_IGD:
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case PCI_PRODUCT_INTEL_82Q33_IGD_1:
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isc->chiptype = CHIP_G33;
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case PCI_PRODUCT_INTEL_82GM45_IGD:
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case PCI_PRODUCT_INTEL_82GM45_IGD_1:
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isc->chiptype = CHIP_G4X;
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break;
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}
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@ -280,12 +299,17 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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case CHIP_G33:
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apbase = AGP_I915_GMADR;
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break;
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case CHIP_I965:
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case CHIP_G4X:
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apbase = AGP_I965_GMADR;
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break;
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default:
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apbase = AGP_I810_GMADR;
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break;
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}
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if (isc->chiptype == CHIP_I965) {
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error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR);
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if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
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error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
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} else {
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error = agp_map_aperture(&isc->vga_pa, sc, apbase);
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}
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@ -313,7 +337,7 @@ agp_i810_attach(device_t parent, device_t self, void *aux)
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agp_generic_detach(sc);
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return error;
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}
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} else if (isc->chiptype == CHIP_I965) {
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} else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
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error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR,
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PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
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&mmadr, &mmadrsize);
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@ -442,90 +466,157 @@ static int agp_i810_init(struct agp_softc *sc)
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gatt->ag_physical = pgtblctl & ~1;
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} else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
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isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) {
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isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
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isc->chiptype == CHIP_G4X) {
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pcireg_t reg;
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u_int32_t pgtblctl, stolen;
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u_int32_t pgtblctl, gtt_size, stolen;
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u_int16_t gcc1;
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);
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gcc1 = (u_int16_t)(reg >> 16);
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pgtblctl = READ4(AGP_I810_PGTBL_CTL);
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/* Stolen memory is set up at the beginning of the aperture by
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* the BIOS, consisting of the GATT followed by 4kb for the
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* BIOS display.
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*/
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switch (isc->chiptype) {
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case CHIP_I855:
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stolen = 128 + 4;
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gtt_size = 128;
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break;
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case CHIP_I915:
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stolen = 256 + 4;
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gtt_size = 256;
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break;
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case CHIP_I965:
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stolen = 512 + 4;
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switch (pgtblctl) {
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case AGP_I810_PGTBL_SIZE_128KB:
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case AGP_I810_PGTBL_SIZE_512KB:
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gtt_size = 512;
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break;
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case AGP_I965_PGTBL_SIZE_1MB:
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gtt_size = 1024;
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break;
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case AGP_I965_PGTBL_SIZE_2MB:
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gtt_size = 1024;
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break;
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case AGP_I965_PGTBL_SIZE_1_5MB:
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gtt_size = 1024;
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break;
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default:
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aprint_error("Bad PGTBL size\n");
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agp_generic_detach(sc);
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return EINVAL;
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}
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break;
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case CHIP_G33:
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switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) {
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case AGP_G33_PGTBL_SIZE_1M:
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stolen = 1024 + 4;
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gtt_size = 1024;
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break;
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case AGP_G33_PGTBL_SIZE_2M:
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stolen = 2048 + 4;
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gtt_size = 2048;
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break;
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default:
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aprint_error(": bad gtt size\n");
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aprint_error(": Bad PGTBL size\n");
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agp_generic_detach(sc);
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return EINVAL;
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}
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break;
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case CHIP_G4X:
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gtt_size = 0;
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break;
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default:
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aprint_error(": bad chiptype\n");
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agp_generic_detach(sc);
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return EINVAL;
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}
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}
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switch (gcc1 & AGP_I855_GCC1_GMS) {
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case AGP_I855_GCC1_GMS_STOLEN_1M:
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isc->stolen = (1024 - stolen) * 1024 / 4096;
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stolen = 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_4M:
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isc->stolen = (4096 - stolen) * 1024 / 4096;
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stolen = 4 * 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_8M:
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isc->stolen = (8192 - stolen) * 1024 / 4096;
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stolen = 8 * 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_16M:
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isc->stolen = (16384 - stolen) * 1024 / 4096;
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stolen = 16 * 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_32M:
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isc->stolen = (32768 - stolen) * 1024 / 4096;
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stolen = 32 * 1024;
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break;
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case AGP_I915_GCC1_GMS_STOLEN_48M:
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isc->stolen = (49152 - stolen) * 1024 / 4096;
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stolen = 48 * 1024;
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break;
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case AGP_I915_GCC1_GMS_STOLEN_64M:
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isc->stolen = (65536 - stolen) * 1024 / 4096;
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stolen = 64 * 1024;
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break;
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case AGP_G33_GCC1_GMS_STOLEN_128M:
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isc->stolen = ((128 * 1024) - stolen) * 1024 / 4096;
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stolen = 128 * 1024;
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break;
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case AGP_G33_GCC1_GMS_STOLEN_256M:
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isc->stolen = ((256 * 1024) - stolen) * 1024 / 4096;
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stolen = 256 * 1024;
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_96M:
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stolen = 96 * 1024;
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_160M:
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stolen = 160 * 1024;
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_224M:
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stolen = 224 * 1024;
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_352M:
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stolen = 352 * 1024;
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break;
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default:
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isc->stolen = 0;
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aprint_error(
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": unknown memory configuration, disabling\n");
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agp_generic_detach(sc);
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return EINVAL;
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}
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switch (gcc1 & AGP_I855_GCC1_GMS) {
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case AGP_I915_GCC1_GMS_STOLEN_48M:
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case AGP_I915_GCC1_GMS_STOLEN_64M:
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if (isc->chiptype != CHIP_I915 &&
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isc->chiptype != CHIP_I965 &&
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isc->chiptype != CHIP_G33 &&
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isc->chiptype != CHIP_G4X)
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stolen = 0;
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break;
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case AGP_G33_GCC1_GMS_STOLEN_128M:
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case AGP_G33_GCC1_GMS_STOLEN_256M:
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if (isc->chiptype != CHIP_I965 &&
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isc->chiptype != CHIP_G33 &&
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isc->chiptype != CHIP_G4X)
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stolen = 0;
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_96M:
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case AGP_G4X_GCC1_GMS_STOLEN_160M:
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case AGP_G4X_GCC1_GMS_STOLEN_224M:
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case AGP_G4X_GCC1_GMS_STOLEN_352M:
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if (isc->chiptype != CHIP_I965 &&
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isc->chiptype != CHIP_G4X)
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stolen = 0;
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break;
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}
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/* BIOS space */
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if (isc->chiptype != CHIP_G4X)
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gtt_size += 4;
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isc->stolen = (stolen - gtt_size) * 1024 / 4096;
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if (isc->stolen > 0) {
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aprint_normal(": detected %dk stolen memory\n%s",
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isc->stolen * 4, device_xname(sc->as_dev));
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}
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/* GATT address is already in there, make sure it's enabled */
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pgtblctl = READ4(AGP_I810_PGTBL_CTL);
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pgtblctl |= 1;
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WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
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@ -579,41 +670,59 @@ agp_i810_get_aperture(struct agp_softc *sc)
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{
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struct agp_i810_softc *isc = sc->as_chipc;
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pcireg_t reg;
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u_int32_t size;
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u_int16_t miscc, gcc1, msac;
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size = 0;
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switch (isc->chiptype) {
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case CHIP_I810:
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
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miscc = (u_int16_t)(reg >> 16);
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if ((miscc & AGP_I810_MISCC_WINSIZE) ==
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AGP_I810_MISCC_WINSIZE_32)
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return 32 * 1024 * 1024;
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size = 32 * 1024 * 1024;
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else
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return 64 * 1024 * 1024;
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size = 64 * 1024 * 1024;
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break;
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case CHIP_I830:
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
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gcc1 = (u_int16_t)(reg >> 16);
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if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
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return 64 * 1024 * 1024;
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size = 64 * 1024 * 1024;
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else
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return 128 * 1024 * 1024;
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size = 128 * 1024 * 1024;
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break;
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case CHIP_I855:
|
||||
return 128 * 1024 * 1024;
|
||||
size = 128 * 1024 * 1024;
|
||||
break;
|
||||
case CHIP_I915:
|
||||
case CHIP_G33:
|
||||
reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC);
|
||||
msac = (u_int16_t)(reg >> 16);
|
||||
if (msac & AGP_I915_MSAC_APER_128M)
|
||||
return 128 * 1024 * 1024;
|
||||
size = 128 * 1024 * 1024;
|
||||
else
|
||||
return 256 * 1024 * 1024;
|
||||
size = 256 * 1024 * 1024;
|
||||
break;
|
||||
case CHIP_I965:
|
||||
return 512 * 1024 * 1024;
|
||||
size = 512 * 1024 * 1024;
|
||||
break;
|
||||
case CHIP_G4X:
|
||||
reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_G4X_MSAC);
|
||||
msac = (u_int16_t)(reg >> 16);
|
||||
switch (msac & AGP_G4X_MSAC_MASK) {
|
||||
case AGP_G4X_MSAC_APER_256M:
|
||||
size = 256 * 1024 * 1024;
|
||||
case AGP_G4X_MSAC_APER_512M:
|
||||
size = 512 * 1024 * 1024;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
aprint_error(": Unknown chipset\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
return size;
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -710,7 +819,7 @@ agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
|
|||
}
|
||||
}
|
||||
|
||||
WRITEGTT(offset, physical | 1);
|
||||
agp_i810_write_gtt_entry(isc, offset, physical | 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -732,7 +841,7 @@ agp_i810_unbind_page(struct agp_softc *sc, off_t offset)
|
|||
}
|
||||
}
|
||||
|
||||
WRITEGTT(offset, 0);
|
||||
agp_i810_write_gtt_entry(isc, offset, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -864,7 +973,7 @@ agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem,
|
|||
}
|
||||
|
||||
if (mem->am_type == 2) {
|
||||
WRITEGTT(offset, mem->am_physical | 1);
|
||||
agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1);
|
||||
mem->am_offset = offset;
|
||||
mem->am_is_bound = 1;
|
||||
return 0;
|
||||
|
|
@ -877,7 +986,7 @@ agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem,
|
|||
return EINVAL;
|
||||
|
||||
for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
|
||||
WRITEGTT(offset, i | 3);
|
||||
agp_i810_write_gtt_entry(isc, offset, i | 3);
|
||||
mem->am_is_bound = 1;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -889,7 +998,7 @@ agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem)
|
|||
u_int32_t i;
|
||||
|
||||
if (mem->am_type == 2) {
|
||||
WRITEGTT(mem->am_offset, 0);
|
||||
agp_i810_write_gtt_entry(isc, mem->am_offset, 0);
|
||||
mem->am_offset = 0;
|
||||
mem->am_is_bound = 0;
|
||||
return 0;
|
||||
|
|
@ -902,7 +1011,7 @@ agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem)
|
|||
return EINVAL;
|
||||
|
||||
for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
|
||||
WRITEGTT(i, 0);
|
||||
agp_i810_write_gtt_entry(isc, i, 0);
|
||||
mem->am_is_bound = 0;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: agpreg.h,v 1.19 2008/03/11 13:36:14 joerg Exp $ */
|
||||
/* $NetBSD: agpreg.h,v 1.20 2008/11/29 23:48:12 christos Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 Doug Rabson
|
||||
|
|
@ -176,10 +176,19 @@
|
|||
* Memory mapped register offsets for i810 chipset.
|
||||
*/
|
||||
#define AGP_I810_PGTBL_CTL 0x2020
|
||||
#define AGP_I810_DRT 0x3000
|
||||
#define AGP_I810_DRT_UNPOPULATED 0x00
|
||||
#define AGP_I810_DRT_POPULATED 0x01
|
||||
#define AGP_I810_GTT 0x10000
|
||||
|
||||
/**
|
||||
* This field determines the actual size of the global GTT on the 965
|
||||
* and G33
|
||||
*/
|
||||
#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
|
||||
#define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
|
||||
#define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
|
||||
#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
|
||||
#define AGP_I810_DRT 0x3000
|
||||
#define AGP_I810_DRT_UNPOPULATED 0x00
|
||||
#define AGP_I810_DRT_POPULATED 0x01
|
||||
#define AGP_I810_GTT 0x10000
|
||||
|
||||
/*
|
||||
* Config registers for i830MG device 0
|
||||
|
|
@ -220,16 +229,16 @@
|
|||
#define AGP_I915_GMADR 0x18
|
||||
#define AGP_I915_GTTADR 0x1c
|
||||
#define AGP_I915_GCC1 0x52
|
||||
#define AGP_I915_GCC1_GMS 0x70
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_0M 0x00
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_1M 0x10
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_8M 0x30
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_16M 0x40
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_32M 0x50
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
|
||||
#define AGP_I915_GCC1_GMS 0x70
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_0M 0x00
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_1M 0x10
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_8M 0x30
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_16M 0x40
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_32M 0x50
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
|
||||
#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
|
||||
#define AGP_I915_MSAC 0x60 /* upper word */
|
||||
#define AGP_I915_MSAC_APER_128M 0x02
|
||||
#define AGP_I915_MSAC_APER_128M 0x02
|
||||
|
||||
/*
|
||||
* Config registers for 965G/965Q
|
||||
|
|
@ -237,7 +246,12 @@
|
|||
#define AGP_I965_MMADR 0x10
|
||||
#define AGP_I965_GMADR 0x18
|
||||
|
||||
#define AGP_I965_GTT 0x80000
|
||||
#define AGP_I965_GTT (512*1024)
|
||||
|
||||
#define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
|
||||
#define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
|
||||
#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
|
||||
|
||||
|
||||
/*
|
||||
* Config registers for G33
|
||||
|
|
@ -249,6 +263,21 @@
|
|||
#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
|
||||
#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
|
||||
|
||||
/*
|
||||
* Config registers for G4X
|
||||
*/
|
||||
#define AGP_G4X_MSAC 0x64 /* upper word */
|
||||
#define AGP_G4X_MSAC_MASK 0xff
|
||||
#define AGP_G4X_MSAC_APER_256M 0x02
|
||||
#define AGP_G4X_MSAC_APER_512M 0x04
|
||||
|
||||
#define AGP_G4X_GTT (2*1024*1024)
|
||||
|
||||
#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
|
||||
#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
|
||||
#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
|
||||
#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
|
||||
|
||||
/*
|
||||
* AMD64 GART registers
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
$NetBSD: pcidevs,v 1.966 2008/11/18 16:12:03 matt Exp $
|
||||
$NetBSD: pcidevs,v 1.967 2008/11/29 23:48:12 christos Exp $
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995, 1996 Christopher G. Demetriou
|
||||
|
|
@ -2521,12 +2521,16 @@ product INTEL 82801H_THERMAL 0x284f 82801H Thermal Controller
|
|||
product INTEL 82801IH_LPC 0x2912 82801IH LPC Interface Bridge
|
||||
product INTEL 82801IO_LPC 0x2914 82801IO LPC Interface Bridge
|
||||
product INTEL 82801IR_LPC 0x2916 82801IR LPC Interface Bridge
|
||||
product INTEL 82801IEM_LPC 0x2917 82801IEM LPC Interface Bridge
|
||||
product INTEL 82801IB_LPC 0x2918 82801IB LPC Interface Bridge
|
||||
product INTEL 82801IM_LPC 0x2919 82801IM LPC Interface Bridge
|
||||
product INTEL 82801I_SATA_1 0x2920 82801I SATA Controller w/ 4 ports
|
||||
product INTEL 82801I_SATA_2 0x2921 82801I SATA Controller w/ 2 ports
|
||||
product INTEL 82801I_SATA_AHCI6 0x2922 82801I AHCI SATA Controller w/ 6 ports
|
||||
product INTEL 82801I_SATA_AHCI4 0x2923 82801I AHCI SATA Controller w/ 4 ports
|
||||
product INTEL 82801I_SATA_3 0x2926 82801I SATA Controller w/ 2 ports
|
||||
product INTEL 82801I_SATA_4 0x2928 82801I Mobile AHCI SATA Controller with 2 ports
|
||||
product INTEL 82801I_SATA_5 0x2929 82801I Mobile AHCI SATA Controller with 4 ports
|
||||
product INTEL 82801I_SMB 0x2930 82801I SMBus Controller
|
||||
product INTEL 82801I_THERMAL 0x2932 82801I Thermal Controller
|
||||
product INTEL 82801I_USB_1 0x2934 82801I USB UHCI Controller
|
||||
|
|
@ -2578,6 +2582,15 @@ product INTEL 82965PM_IGD_1 0x2a03 82965PM Integrated Graphics Device
|
|||
product INTEL 82965PM_MEI 0x2a04 82965PM MEI Controller
|
||||
product INTEL 82965PM_IDE 0x2a06 82965PM IDE Interface
|
||||
product INTEL 82965PM_KT 0x2a07 82965PM Serial Interface
|
||||
product INTEL 82GM45_HB 0x2a40 82GM45 Host Bridge
|
||||
product INTEL 82GM45_IGD 0x2a42 82GM45 Integrated Graphics Device
|
||||
product INTEL 82GM45_IGD_1 0x2a43 82GM45 Integrated Graphics Device
|
||||
product INTEL 82IGD_E_HB 0x2e00 82IGD_E Host Bridge
|
||||
product INTEL 82IGD_E_IGD 0x2e02 82IGD_E Integrated Graphics
|
||||
product INTEL 82Q45_HB 0x2e10 82Q45 Host Bridge
|
||||
product INTEL 82Q45_IGD 0x2e12 82Q45 Integrated Graphics Device
|
||||
product INTEL 82G45_HB 0x2e20 82G45 Host Bridge
|
||||
product INTEL 82G45_IGD 0x2e22 82G45 Integrated Graphics Device
|
||||
product INTEL 31244 0x3200 31244 Serial ATA Controller
|
||||
product INTEL 82855PM_DDR 0x3340 82855PM MCH Host Controller
|
||||
product INTEL 82855PM_AGP 0x3341 82855PM Host-AGP Bridge
|
||||
|
|
|
|||
Loading…
Reference in New Issue