allow configuring multiple CPUs (still needs work).
Detect boot page on MP e500 CPUs (P2020, MPC8572, etc) and prevent use of that page in NetBSD. This page is used to communicate with u-boot to spin up secondary CPUs. Probe LBC before PCI so that LBC attached devices can be configured before probing the PCI. This gives a chance to download/setup PCI Express switches before probing/configuring PCI. Fix PIXIS speed entry bug/typo. Rework SYS_CLK logic so that the SYS_CLK config option has the highest priority.
This commit is contained in:
matt
parent
33d93c8dcc
commit
784a196541
@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.5 2011/02/17 13:57:12 matt Exp $ */
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/* $NetBSD: machdep.c,v 1.6 2011/05/28 05:21:40 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -136,10 +136,15 @@ struct powerpc_bus_space gur_le_bst = {
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const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE);
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#if defined(SYS_CLK)
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static uint64_t e500_sys_clk = SYS_CLK;
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#endif
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#ifdef CADMUS
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static uint8_t cadmus_pci;
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static uint8_t cadmus_csr;
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#ifndef SYS_CLK
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static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */
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#endif
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#elif defined(PIXIS)
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static const uint32_t pixis_spd_map[8] = {
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[PX_SPD_33MHZ] = 33333333,
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@ -147,15 +152,15 @@ static const uint32_t pixis_spd_map[8] = {
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[PX_SPD_50MHZ] = 50000000,
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[PX_SPD_66MHZ] = 66666666,
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[PX_SPD_83MHZ] = 83333333,
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[PX_SPD_133MHZ] = 100000000,
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[PX_SPD_100MHZ] = 100000000,
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[PX_SPD_133MHZ] = 133333333,
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[PX_SPD_166MHZ] = 166666667,
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};
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static uint8_t pixis_spd;
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#ifndef SYS_CLK
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static uint64_t e500_sys_clk;
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#elif defined(SYS_CLK)
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static uint64_t e500_sys_clk = SYS_CLK;
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#else
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#endif
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#elif !defined(SYS_CLK)
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static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */
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#endif
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@ -172,7 +177,14 @@ static struct consdev e500_earlycons = {
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* List of port-specific devices to attach to the processor local bus.
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*/
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static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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{ "cpu" }, /* not a real device */
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{ "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */
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{ 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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#if defined(MPC8572) || defined(P2020)
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{ "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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{ "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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#endif
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{ "wdog" }, /* not a real device */
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{ "duart", DUART1_BASE, 2*DUART_SIZE, 0,
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1, { ISOURCE_DUART },
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@ -234,6 +246,9 @@ static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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1 + ilog2(DEVDISR_DDR2_14),
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{ SVR_MPC8572v1 >> 16 } },
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#endif
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{ "lbc", LBC_BASE, LBC_SIZE, 0,
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1, { ISOURCE_LBC },
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1 + ilog2(DEVDISR_LBC) },
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#if defined(MPC8544) || defined(MPC8536)
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{ "pcie", PCIE1_BASE, PCI_SIZE, 1,
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1, { ISOURCE_PCIEX },
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@ -322,9 +337,6 @@ static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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1 + ilog2(DEVDISR_ESDHC_10),
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{ SVR_P2020v2 >> 16 }, },
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#endif
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{ "lbc", LBC_BASE, LBC_SIZE, 0,
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1, { ISOURCE_LBC },
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1 + ilog2(DEVDISR_LBC) },
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//{ "sec", RNG_BASE, RNG_SIZE, 0, 0, },
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{ NULL }
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};
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@ -380,6 +392,16 @@ static psize_t
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memprobe(vaddr_t endkernel)
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{
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phys_ram_seg_t *mr;
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paddr_t boot_page = cpu_read_4(GUR_BPTR);
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printf(" bptr=%"PRIxPADDR, boot_page);
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if (boot_page & BPTR_EN) {
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/*
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* shift it to an address
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*/
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boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT;
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} else {
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boot_page = ~(paddr_t)0;
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}
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/*
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* First we need to find out how much physical memory we have.
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@ -392,8 +414,14 @@ memprobe(vaddr_t endkernel)
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uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i));
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if (v & CS_CONFIG_EN) {
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v = cpu_read_4(DDRC1_BASE + CS_BNDS(i));
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if (v == 0)
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continue;
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mr->start = BNDS_SA_GET(v);
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mr->size = BNDS_SIZE_GET(v);
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#if 0
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printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}",
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mr - physmemr, mr->size, mr->start);
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#endif
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mr++;
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}
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}
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@ -442,6 +470,38 @@ memprobe(vaddr_t endkernel)
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availmemr[0].size -= endkernel - availmemr[0].start;
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availmemr[0].start = endkernel;
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mr = availmemr;
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for (u_int i = 0; i < cnt; i++, mr++) {
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/*
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* U-boot reserves a boot-page on multi-core chips.
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* We need to make sure that we never disturb it.
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*/
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const paddr_t mr_end = mr->start + mr->size;
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if (mr_end > boot_page && boot_page >= mr->start) {
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/*
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* Normally u-boot will put in at the end
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* of memory. But in case it doesn't, deal
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* with all possibilities.
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*/
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if (boot_page + PAGE_SIZE == mr_end) {
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mr->size -= PAGE_SIZE;
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} else if (boot_page == mr->start) {
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mr->start += PAGE_SIZE;
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mr->size -= PAGE_SIZE;
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} else {
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mr->size = boot_page - mr->start;
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mr++;
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for (u_int j = cnt; j > i + 1; j--) {
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availmemr[j] = availmemr[j-1];
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}
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cnt++;
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mr->start = boot_page + PAGE_SIZE;
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mr->size = mr_end - mr->start;
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}
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break;
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}
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}
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/*
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* Steal pages at the end of memory for the kernel message buffer.
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*/
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@ -577,20 +637,26 @@ e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg)
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static void
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e500_cpu_attach(device_t self, u_int instance)
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{
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struct cpu_info * const ci = &cpu_info[instance];
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KASSERT(instance == 0);
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self->dv_private = ci;
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struct cpu_info * const ci = &cpu_info[instance - (instance > 0)];
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ci->ci_cpuid = instance;
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ci->ci_dev = self;
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//ci->ci_idlespin = cpu_idlespin;
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if (instance > 0) {
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if (instance > 1) {
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#ifdef MULTIPROCESSOR
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#error still needs to be written
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ci->ci_idepth = -1;
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cpu_probe_cache();
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#else
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aprint_error_dev(self, "disabled (uniprocessor kernel)\n");
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return;
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#endif
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}
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self->dv_private = ci;
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ci->ci_cpuid = instance - (instance > 0);
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ci->ci_dev = self;
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//ci->ci_idlespin = cpu_idlespin;
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uint64_t freq = board_info_get_number("processor-frequency");
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char freqbuf[10];
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if (freq >= 999500000) {
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const uint32_t freq32 = (freq + 500000) / 10000000;
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@ -681,8 +747,13 @@ initppc(vaddr_t startkernel, vaddr_t endkernel)
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#endif
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#ifdef PIXIS
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pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD];
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printf(" pixis_spd=%#x ", pixis_spd);
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printf(" pixis_spd=%#x sysclk=%"PRIuMAX,
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pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd));
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#ifndef SYS_CLK
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e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)];
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#else
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printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]);
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#endif
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#endif
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printf(" porpllsr=0x%08x",
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*(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR));
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@ -734,7 +805,7 @@ initppc(vaddr_t startkernel, vaddr_t endkernel)
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* Get the cache sizes.
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*/
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cpu_probe_cache();
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printf(" cache(DC=%u/%u,IC=%u/%u)",
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printf(" cache(DC=%uKB/%u,IC=%uKB/%u)",
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ci->ci_ci.dcache_size >> 10,
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ci->ci_ci.dcache_line_size,
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ci->ci_ci.icache_size >> 10,
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@ -962,6 +1033,32 @@ cpu_startup(void)
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l2banks >>= 1;
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}
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#endif
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paddr_t boot_page = cpu_read_4(GUR_BPTR);
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if (boot_page & BPTR_EN) {
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bool found = false;
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boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT;
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for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4),
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* const bp = (void *)boot_page;
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bp <= dp; dp--) {
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if (*dp == boot_page) {
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uintptr_t spinup_table_addr = (uintptr_t)++dp;
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spinup_table_addr =
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roundup2(spinup_table_addr, 32);
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board_info_add_number("mp-boot-page",
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boot_page);
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board_info_add_number("mp-spin-up-table",
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spinup_table_addr);
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printf("Found MP boot page @ %#"PRIxPADDR". "
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"Spin-up table @ %#"PRIxPTR"\n",
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boot_page, spinup_table_addr);
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found = true;
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break;
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}
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}
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if (!found)
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printf("Found MP boot page @ %#"PRIxPADDR
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" with missing U-boot signature!\n", boot_page);
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}
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board_info_add_number("l2-cache-size", l2siz);
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board_info_add_number("l2-cache-line-size", 32);
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board_info_add_number("l2-cache-banks", l2banks);
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